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Searched refs:Orn (Results 1 – 16 of 16) sorted by relevance

/external/vixl/test/aarch32/
Dtest-disasm-a32.cc413 COMPARE_BOTH(Orn(r0, r1, 0), "mvn r0, #0\n"); in TEST()
414 COMPARE_BOTH(Orn(r0, r0, 0xffffffff), ""); in TEST()
420 COMPARE_A32(Orn(r0, r1, 1), in TEST()
429 COMPARE_BOTH(Orn(r0, r1, 0x00ffffff), "orr r0, r1, #0xff000000\n"); in TEST()
430 COMPARE_BOTH(Orn(r0, r1, 0xff00ffff), "orr r0, r1, #0xff0000\n"); in TEST()
438 COMPARE_T32(Orn(r0, r1, 0xabcd2345), in TEST()
447 COMPARE_A32(Orn(r0, r1, r2), in TEST()
451 COMPARE_A32(Orn(r0, r0, r1), in TEST()
455 COMPARE_A32(Orn(r0, r1, r0), in TEST()
459 COMPARE_A32(Orn(r0, r0, r0), in TEST()
[all …]
Dtest-simulator-cond-rd-rn-operand-rm-t32.cc126 M(Orn) \
Dtest-simulator-cond-rd-rn-operand-const-t32.cc126 M(Orn) \
Dtest-simulator-cond-rd-rn-operand-rm-shift-amount-1to31-t32.cc126 M(Orn) \
Dtest-simulator-cond-rd-rn-operand-rm-shift-amount-1to32-t32.cc126 M(Orn) \
Dtest-assembler-aarch32.cc3267 __ Orn(r0, r0, 0xffffffff); in TEST() local
3311 __ Orn(r4, r0, 0); in TEST() local
/external/vixl/test/aarch64/
Dtest-assembler-aarch64.cc797 __ Orn(x2, x0, Operand(x1)); in TEST() local
798 __ Orn(w3, w0, Operand(w1, LSL, 4)); in TEST() local
799 __ Orn(x4, x0, Operand(x1, LSL, 4)); in TEST() local
800 __ Orn(x5, x0, Operand(x1, LSR, 1)); in TEST() local
801 __ Orn(w6, w0, Operand(w1, ASR, 1)); in TEST() local
802 __ Orn(x7, x0, Operand(x1, ASR, 1)); in TEST() local
803 __ Orn(w8, w0, Operand(w1, ROR, 16)); in TEST() local
804 __ Orn(x9, x0, Operand(x1, ROR, 16)); in TEST() local
805 __ Orn(w10, w0, 0x0000ffff); in TEST() local
806 __ Orn(x11, x0, 0x0000ffff0000ffff); in TEST() local
[all …]
Dtest-disasm-aarch64.cc2992 COMPARE_MACRO(Orn(w8, w9, 0), "mov w8, #0xffffffff"); in TEST()
2993 COMPARE_MACRO(Orn(x8, x9, 0), "mov x8, #0xffffffffffffffff"); in TEST()
3010 COMPARE_MACRO(Orn(w20, w21, 0xffffffff), "mov w20, w21"); in TEST()
3011 COMPARE_MACRO(Orn(x20, x21, 0xffffffff), "orr x20, x21, #0xffffffff00000000"); in TEST()
3012 COMPARE_MACRO(Orn(x20, x21, 0xffffffffffffffff), "mov x20, x21"); in TEST()
4522 COMPARE_MACRO(Orn(v6.V8B(), v7.V8B(), v8.V8B()), "orn v6.8b, v7.8b, v8.8b"); in TEST()
4523 COMPARE_MACRO(Orn(v6.V16B(), v7.V16B(), v8.V16B()), in TEST()
/external/v8/src/compiler/arm64/
Dcode-generator-arm64.cc1079 __ Orn(i.OutputRegister(), i.InputOrZeroRegister64(0), in AssembleArchInstruction() local
1083 __ Orn(i.OutputRegister32(), i.InputOrZeroRegister32(0), in AssembleArchInstruction() local
/external/v8/src/arm64/
Dmacro-assembler-arm64-inl.h98 void MacroAssembler::Orn(const Register& rd, in Orn() function
Dmacro-assembler-arm64.h189 inline void Orn(const Register& rd,
/external/vixl/src/aarch64/
Dmacro-assembler-aarch64.h653 void Orn(const Register& rd, const Register& rn, const Operand& operand);
2194 V(orn, Orn) \
Dmacro-assembler-aarch64.cc776 void MacroAssembler::Orn(const Register& rd, in Orn() function in vixl::aarch64::MacroAssembler
/external/vixl/src/aarch32/
Dmacro-assembler-aarch32.h2690 void Orn(Condition cond, Register rd, Register rn, const Operand& operand) { in Orn() function
2710 void Orn(Register rd, Register rn, const Operand& operand) { in Orn() function
2711 Orn(al, rd, rn, operand); in Orn()
2713 void Orn(FlagsUpdate flags, in Orn() function
2720 Orn(cond, rd, rn, operand); in Orn()
2726 Orn(cond, rd, rn, operand); in Orn()
2730 void Orn(FlagsUpdate flags, in Orn() function
2734 Orn(flags, al, rd, rn, operand); in Orn()
/external/honggfuzz/examples/apache-httpd/corpus_http2/
D6180cf3b976517a9957010cbbec7b2e3.0000e9bf.honggfuzz.cov18 �/��8��H�Orn<�J7�d��<Ƿj iG�b1@��SC%8hv��˨G���g����TKY����vM�{&(qA�̮�>X3[f�y��z� ���S…
/external/llvm/test/MC/Disassembler/AArch64/
Dneon-instructions.txt44 # Vector And, Orr, Eor, Orn, Bic