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Searched refs:PIPE_CONTROL_DATA_CACHE_FLUSH (Results 1 – 5 of 5) sorted by relevance

/external/mesa3d/src/mesa/drivers/dri/i965/
Dgen7_l3_state.c86 PIPE_CONTROL_DATA_CACHE_FLUSH | in setup_l3_config()
115 PIPE_CONTROL_DATA_CACHE_FLUSH | in setup_l3_config()
Dbrw_pipe_control.c54 PIPE_CONTROL_DATA_CACHE_FLUSH; in gen8_add_cs_stall_workaround_bits()
Dbrw_program.c296 unsigned bits = (PIPE_CONTROL_DATA_CACHE_FLUSH | in brw_memory_barrier()
Dbrw_defines.h3089 #define PIPE_CONTROL_DATA_CACHE_FLUSH (1 << 5) macro
3099 (PIPE_CONTROL_DEPTH_CACHE_FLUSH | PIPE_CONTROL_DATA_CACHE_FLUSH | \
Dbrw_misc_state.c894 brw->gen >= 7 ? PIPE_CONTROL_DATA_CACHE_FLUSH : 0; in brw_emit_select_pipeline()