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Searched refs:PIPE_CONTROL_STATE_CACHE_INVALIDATE (Results 1 – 5 of 5) sorted by relevance

/external/mesa3d/src/mesa/drivers/dri/i965/
Dbrw_binding_tables.c353 brw_emit_pipe_control_flush(brw, PIPE_CONTROL_STATE_CACHE_INVALIDATE); in gen7_disable_hw_binding_tables()
400 brw_emit_pipe_control_flush(brw, PIPE_CONTROL_STATE_CACHE_INVALIDATE); in gen7_enable_hw_binding_tables()
Dgen6_vs_state.c169 PIPE_CONTROL_STATE_CACHE_INVALIDATE); in upload_vs_state()
Dgen7_l3_state.c108 PIPE_CONTROL_STATE_CACHE_INVALIDATE | in setup_l3_config()
Dbrw_defines.h3092 #define PIPE_CONTROL_STATE_CACHE_INVALIDATE (1 << 2) macro
3103 (PIPE_CONTROL_STATE_CACHE_INVALIDATE | PIPE_CONTROL_CONST_CACHE_INVALIDATE | \
Dbrw_misc_state.c906 PIPE_CONTROL_STATE_CACHE_INVALIDATE | in brw_emit_select_pipeline()