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Searched refs:PredReg (Results 1 – 25 of 41) sorted by relevance

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/external/swiftshader/third_party/LLVM/lib/Target/ARM/
DARMLoadStoreOptimizer.cpp92 ARMCC::CondCodes Pred, unsigned PredReg, unsigned Scratch,
104 unsigned PredReg,
110 ARMCC::CondCodes Pred, unsigned PredReg,
293 unsigned PredReg, unsigned Scratch, DebugLoc dl, in MergeOps() argument
346 .addImm(Pred).addReg(PredReg).addReg(0); in MergeOps()
357 .addImm(Pred).addReg(PredReg); in MergeOps()
373 ARMCC::CondCodes Pred, unsigned PredReg, in MergeOpsUpdate() argument
408 Pred, PredReg, Scratch, dl, Regs)) in MergeOpsUpdate()
440 ARMCC::CondCodes Pred, unsigned PredReg, in MergeLDR_STR() argument
493 Base, false, Opcode, Pred, PredReg, Scratch, dl, Merges); in MergeLDR_STR()
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DThumb2InstrInfo.cpp55 unsigned PredReg = 0; in ReplaceTailWithBranchTo() local
56 ARMCC::CondCodes CC = llvm::getInstrPredicate(Tail, PredReg); in ReplaceTailWithBranchTo()
103 unsigned PredReg = 0; in isLegalToSplitMBBAt() local
104 return llvm::getITInstrPredicate(MBBI, PredReg) == ARMCC::AL; in isLegalToSplitMBBAt()
177 ARMCC::CondCodes Pred, unsigned PredReg, in emitT2RegPlusImmediate() argument
192 .addImm((unsigned)Pred).addReg(PredReg).setMIFlags(MIFlags); in emitT2RegPlusImmediate()
199 .addImm((unsigned)Pred).addReg(PredReg).setMIFlags(MIFlags); in emitT2RegPlusImmediate()
208 .addImm((unsigned)Pred).addReg(PredReg).addReg(0) in emitT2RegPlusImmediate()
214 .addImm((unsigned)Pred).addReg(PredReg).addReg(0) in emitT2RegPlusImmediate()
400 unsigned PredReg; in rewriteT2FrameIndex() local
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DARMBaseRegisterInfo.cpp804 unsigned PredReg, unsigned MIFlags) const { in emitLoadConstPool() argument
814 .addImm(0).addImm(Pred).addReg(PredReg) in emitLoadConstPool()
838 ARMCC::CondCodes Pred = ARMCC::AL, unsigned PredReg = 0) { in emitSPUpdate() argument
841 Pred, PredReg, TII); in emitSPUpdate()
844 Pred, PredReg, TII); in emitSPUpdate()
878 unsigned PredReg = Old->getOperand(2).getReg(); in eliminateCallFramePseudoInstr() local
879 emitSPUpdate(isARM, MBB, I, dl, TII, -Amount, Pred, PredReg); in eliminateCallFramePseudoInstr()
882 unsigned PredReg = Old->getOperand(3).getReg(); in eliminateCallFramePseudoInstr() local
884 emitSPUpdate(isARM, MBB, I, dl, TII, Amount, Pred, PredReg); in eliminateCallFramePseudoInstr()
1204 unsigned PredReg = (PIdx == -1) ? 0 : MI.getOperand(PIdx+1).getReg(); in eliminateFrameIndex() local
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DMLxExpansionPass.cpp219 unsigned PredReg = MI->getOperand(++NextOp).getReg(); in ExpandFPMLxInstruction() local
230 MIB.addImm(Pred).addReg(PredReg); in ExpandFPMLxInstruction()
242 MIB.addImm(Pred).addReg(PredReg); in ExpandFPMLxInstruction()
DARMBaseInstrInfo.h338 ARMCC::CondCodes getInstrPredicate(const MachineInstr *MI, unsigned &PredReg);
354 ARMCC::CondCodes Pred, unsigned PredReg,
360 ARMCC::CondCodes Pred, unsigned PredReg,
DThumb2SizeReduction.cpp533 unsigned PredReg = 0; in ReduceSpecial() local
534 if (getInstrPredicate(MI, PredReg) == ARMCC::AL) { in ReduceSpecial()
614 unsigned PredReg = 0; in ReduceTo2Addr() local
615 ARMCC::CondCodes Pred = getInstrPredicate(MI, PredReg); in ReduceTo2Addr()
705 unsigned PredReg = 0; in ReduceToNarrow() local
706 ARMCC::CondCodes Pred = getInstrPredicate(MI, PredReg); in ReduceToNarrow()
DThumb2RegisterInfo.h38 unsigned PredReg = 0,
DThumb2ITBlockPass.cpp172 unsigned PredReg = 0; in InsertITInstructions() local
173 ARMCC::CondCodes CC = llvm::getITInstrPredicate(MI, PredReg); in InsertITInstructions()
DThumb2RegisterInfo.cpp40 ARMCC::CondCodes Pred, unsigned PredReg, in emitLoadConstPool() argument
DThumb2InstrInfo.h73 ARMCC::CondCodes getITInstrPredicate(const MachineInstr *MI, unsigned &PredReg);
DThumb1RegisterInfo.h43 unsigned PredReg = 0,
DThumb1RegisterInfo.cpp69 ARMCC::CondCodes Pred, unsigned PredReg, in emitLoadConstPool() argument
79 .addConstantPoolIndex(Idx).addImm(Pred).addReg(PredReg) in emitLoadConstPool()
412 unsigned PredReg; in rewriteFrameIndex() local
413 if (Offset == 0 && getInstrPredicate(&MI, PredReg) == ARMCC::AL) { in rewriteFrameIndex()
/external/llvm/lib/Target/ARM/
DARMLoadStoreOptimizer.cpp150 ARMCC::CondCodes Pred, unsigned PredReg);
154 ARMCC::CondCodes Pred, unsigned PredReg, const DebugLoc &DL,
159 ARMCC::CondCodes Pred, unsigned PredReg, const DebugLoc &DL,
460 unsigned PredReg) { in UpdateBaseRegUses() argument
528 .addReg(Base).addImm(WordOffset * 4).addImm(Pred).addReg(PredReg); in UpdateBaseRegUses()
546 .addReg(Base).addImm(WordOffset * 4).addImm(Pred).addReg(PredReg); in UpdateBaseRegUses()
596 ARMCC::CondCodes Pred, unsigned PredReg, const DebugLoc &DL, in CreateLoadStoreMulti() argument
711 .addImm(Pred).addReg(PredReg); in CreateLoadStoreMulti()
721 .addImm(Pred).addReg(PredReg); in CreateLoadStoreMulti()
726 .addImm(Pred).addReg(PredReg); in CreateLoadStoreMulti()
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DThumb2InstrInfo.cpp60 unsigned PredReg = 0; in ReplaceTailWithBranchTo() local
61 ARMCC::CondCodes CC = getInstrPredicate(*Tail, PredReg); in ReplaceTailWithBranchTo()
108 unsigned PredReg = 0; in isLegalToSplitMBBAt() local
109 return getITInstrPredicate(*MBBI, PredReg) == ARMCC::AL; in isLegalToSplitMBBAt()
225 ARMCC::CondCodes Pred, unsigned PredReg, in emitT2RegPlusImmediate() argument
231 .addImm((unsigned)Pred).addReg(PredReg).setMIFlags(MIFlags); in emitT2RegPlusImmediate()
248 .addImm((unsigned)Pred).addReg(PredReg).setMIFlags(MIFlags); in emitT2RegPlusImmediate()
255 .addImm((unsigned)Pred).addReg(PredReg).setMIFlags(MIFlags); in emitT2RegPlusImmediate()
264 .addImm((unsigned)Pred).addReg(PredReg).addReg(0) in emitT2RegPlusImmediate()
275 .addImm((unsigned)Pred).addReg(PredReg).addReg(0) in emitT2RegPlusImmediate()
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DThumbRegisterInfo.cpp66 ARMCC::CondCodes Pred, unsigned PredReg, in emitThumb1LoadConstPool() argument
78 .addConstantPoolIndex(Idx).addImm(Pred).addReg(PredReg) in emitThumb1LoadConstPool()
86 ARMCC::CondCodes Pred, unsigned PredReg, in emitThumb2LoadConstPool() argument
106 ARMCC::CondCodes Pred, unsigned PredReg, unsigned MIFlags) const { in emitLoadConstPool() argument
113 PredReg, MIFlags); in emitLoadConstPool()
116 PredReg, MIFlags); in emitLoadConstPool()
DThumb2SizeReduction.cpp441 unsigned PredReg = MI->getOperand(5).getReg(); in ReduceLoadStore() local
454 .addReg(PredReg) in ReduceLoadStore()
647 unsigned PredReg = 0; in ReduceSpecial() local
648 if (getInstrPredicate(*MI, PredReg) == ARMCC::AL) { in ReduceSpecial()
752 unsigned PredReg = 0; in ReduceTo2Addr() local
753 ARMCC::CondCodes Pred = getInstrPredicate(*MI, PredReg); in ReduceTo2Addr()
848 unsigned PredReg = 0; in ReduceToNarrow() local
849 ARMCC::CondCodes Pred = getInstrPredicate(*MI, PredReg); in ReduceToNarrow()
DMLxExpansionPass.cpp285 unsigned PredReg = MI->getOperand(++NextOp).getReg(); in ExpandFPMLxInstruction() local
298 MIB.addImm(Pred).addReg(PredReg); in ExpandFPMLxInstruction()
310 MIB.addImm(Pred).addReg(PredReg); in ExpandFPMLxInstruction()
DARMBaseRegisterInfo.cpp414 ARMCC::CondCodes Pred, unsigned PredReg, unsigned MIFlags) const { in emitLoadConstPool() argument
425 .addImm(0).addImm(Pred).addReg(PredReg) in emitLoadConstPool()
764 unsigned PredReg = (PIdx == -1) ? 0 : MI.getOperand(PIdx+1).getReg(); in eliminateFrameIndex() local
772 Offset, Pred, PredReg, TII); in eliminateFrameIndex()
776 Offset, Pred, PredReg, TII); in eliminateFrameIndex()
DARMBaseInstrInfo.h454 ARMCC::CondCodes getInstrPredicate(const MachineInstr &MI, unsigned &PredReg);
476 ARMCC::CondCodes Pred, unsigned PredReg,
483 ARMCC::CondCodes Pred, unsigned PredReg,
DThumbRegisterInfo.h44 unsigned PredReg = 0,
DThumb2InstrInfo.h71 ARMCC::CondCodes getITInstrPredicate(const MachineInstr &MI, unsigned &PredReg);
DThumb2ITBlockPass.cpp189 unsigned PredReg = 0; in InsertITInstructions() local
190 ARMCC::CondCodes CC = getITInstrPredicate(*MI, PredReg); in InsertITInstructions()
/external/llvm/lib/Target/Hexagon/MCTargetDesc/
DHexagonMCChecker.cpp58 unsigned PredReg = Hexagon::NoRegister; in init() local
68 PredReg = R; in init()
73 NewPreds.insert(PredReg); in init()
112 Defs[R].insert(PredSense(PredReg, isTrue)); in init()
156 CurDefs.insert(*SRI), Defs[*SRI].insert(PredSense(PredReg, isTrue)); in init()
169 Defs[*SRI].insert(PredSense(PredReg, isTrue)); in init()
185 … NewDefs[*SRI].push_back(NewSense::Def(PredReg, HexagonMCInstrInfo::isPredicatedTrue(MCII, MCI), in init()
197 … NewDefs[*SRI].push_back(NewSense::Def(PredReg, HexagonMCInstrInfo::isPredicatedTrue(MCII, MCI), in init()
221 NewUses[N] = NewSense::Use(PredReg, HexagonMCInstrInfo::isPredicatedTrue(MCII, MCI)); in init()
564 if (Use.IsNVJ && (Def.IsFloat || Def.PredReg != 0)) in hasValidNewValueDef()
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DHexagonMCCompound.cpp182 unsigned PredReg = Predicate.getReg(); in getCompoundOp() local
184 assert((PredReg == Hexagon::P0) || (PredReg == Hexagon::P1) || in getCompoundOp()
185 (PredReg == Hexagon::P2) || (PredReg == Hexagon::P3)); in getCompoundOp()
192 return (PredReg == Hexagon::P0) ? fp0_jump_nt : fp1_jump_nt; in getCompoundOp()
194 return (PredReg == Hexagon::P0) ? fp0_jump_t : fp1_jump_t; in getCompoundOp()
196 return (PredReg == Hexagon::P0) ? tp0_jump_nt : tp1_jump_nt; in getCompoundOp()
198 return (PredReg == Hexagon::P0) ? tp0_jump_t : tp1_jump_t; in getCompoundOp()
/external/llvm/lib/Target/Hexagon/
DHexagonGenPredicate.cpp95 bool isScalarPred(Register PredReg);
302 bool HexagonGenPredicate::isScalarPred(Register PredReg) { in isScalarPred() argument
304 WorkQ.push(PredReg); in isScalarPred()

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