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/external/libxaac/decoder/armv7/
Dixheaacd_post_twiddle_overlap.s141 VMULL.S32 Q0, D2, D0
142 VQMOVN.S64 D8, Q0
191 VLD2.32 {Q0, Q1}, [R1], R12
195 VREV64.16 Q0, Q0
251 VMULL.U16 Q0, D26, D18
257 VSHR.U32 Q0, Q0, #16
259 VMLAL.S16 Q0, D27, D18
265 VADD.I32 Q14, Q14, Q0
268 VMULL.U16 Q0, D6, D9
272 VSHR.S32 Q0, Q0, #16
[all …]
Dia_xheaacd_mps_reoder_mulshift_acc.s45 VLD1.32 {Q0, Q1}, [R8]
47 VST1.32 {Q0, Q1}, [R7]
59 VLD1.32 {Q0, Q1}, [R8]! @LOADING values from R0 Sr_fix
69 VMULL.S32 Q0, D4, D12
74 VSHR.S64 Q0, Q0, #31
84 VSUB.I64 Q12, Q12, Q0
103 VLD1.32 {Q0, Q1}, [R8]! @LOADING values from R0 Sr_fix
113 VMULL.S32 Q0, D4, D12
123 VSHR.S64 Q0, Q0, #31
128 VSUB.I64 Q12, Q12, Q0
[all …]
Dixheaacd_post_twiddle.s157 VMULL.U16 Q0, D26, D10
173 VSHR.U32 Q0, Q0, #16
179 VMLAL.S16 Q0, D27, D10
187 VNEG.S32 Q0, Q0
189 VADD.I32 Q13, Q14, Q0
265 VMULL.U16 Q0, D26, D10
281 VSHR.U32 Q0, Q0, #16
287 VMLAL.S16 Q0, D27, D10
295 VNEG.S32 Q0, Q0
297 VADD.I32 Q13, Q14, Q0
[all …]
Dixheaacd_overlap_add1.s51 VQNEG.S32 Q0, Q3
101 VMULL.S32 Q0, D14, D4
102 VQMOVN.S64 D16, Q0
103 VMULL.S32 Q0, D15, D5
104 VQMOVN.S64 D17, Q0
108 VQNEG.S32 Q0, Q3
155 VMULL.S32 Q0, D4, D14
156 VQMOVN.S64 D16, Q0
157 VMULL.S32 Q0, D5, D15
158 VQMOVN.S64 D17, Q0
[all …]
Dixheaacd_dct3_32.s53 VLD1.32 {Q0}, [R6]!
61 VSHR.S32 Q0, Q0, #7
65 VADD.I32 Q2, Q1, Q0
80 VLD1.32 {Q0}, [R6]!
90 VSHR.S32 Q0, Q0, #7
103 VADD.I32 Q2, Q1, Q0
131 VLD1.32 {Q0}, [R6]!
140 VSHR.S32 Q0, Q0, #7
158 VADD.I32 Q2, Q1, Q0
194 VSHR.S32 Q0, Q0, #7
[all …]
Dixheaacd_esbr_fwd_modulation.s40 VSHR.S32 Q0, Q0, #4
51 VQSUB.S32 Q4, Q0, Q2
54 VADD.S32 Q6, Q0, Q2
90 VADD.I64 Q0, Q2, Q5
93 VSHRN.I64 D0, Q0, #31
Dixheaacd_no_lap1.s41 VQNEG.S32 Q0, Q0
45 VQSHL.S32 Q15, Q0, Q1
64 VQNEG.S32 Q0, Q0
72 VQSHL.S32 Q15, Q0, Q1
Dixheaacd_dec_DCT2_64_asm.s45 VLD2.32 {Q0, Q1}, [R0]!
48 VST1.32 {Q0}, [R1]!
85 VLD2.32 {Q0, Q1}, [R0]!
100 VSUB.I32 Q9, Q0, Q2
102 VADD.I32 Q8, Q0, Q2
115 VLD2.32 {Q0, Q1}, [R0]!
147 VSUB.I32 Q9, Q0, Q2
149 VADD.I32 Q8, Q0, Q2
160 VLD2.32 {Q0, Q1}, [R0]!
192 VSUB.I32 Q9, Q0, Q2
[all …]
Dixheaacd_esbr_cos_sin_mod_loop1.s57 VSHRN.I64 D0, Q0, #32
80 VADD.I64 Q0, Q5, Q2
83 VSHRN.I64 D0, Q0, #32
109 VSHRN.I64 D0, Q0, #32
132 VADD.I64 Q0, Q5, Q2
135 VSHRN.I64 D0, Q0, #32
Dixheaacd_calcmaxspectralline.s38 VABS.S32 Q0, Q0
44 VORR Q3, Q0, Q3
Dixheaacd_pre_twiddle_compute.s116 VREV64.16 Q0, Q0
178 VREV64.16 Q0, Q0
244 VREV64.16 Q0, Q0
326 VREV64.16 Q0, Q0
Dixheaacd_calc_post_twid.s66 VNEG.S32 Q0, Q0
Dixheaacd_overlap_add2.s209 VREV64.32 Q0, Q3
210 VQNEG.S32 Q0, Q0
/external/llvm/test/CodeGen/ARM/
Dvldm-liveness.ll4 ; s1 = VLDRS [r0, 1], Q0<imp-def>
5 ; s3 = VLDRS [r0, 2], Q0<imp-use,kill>, Q0<imp-def>
6 ; s0 = VLDRS [r0, 0], Q0<imp-use,kill>, Q0<imp-def>
7 ; s2 = VLDRS [r0, 4], Q0<imp-use,kill>, Q0<imp-def>
11 ; imp-use of Q0, which is undefined.
D2010-06-29-PartialRedefFastAlloc.ll10 ; %reg1028 gets allocated %Q0, and if %reg1030 is reloaded for the partial
11 ; redef, it cannot also get %Q0.
/external/llvm/lib/Target/AArch64/
DAArch64CallingConvention.td68 [Q0, Q1, Q2, Q3, Q4, Q5, Q6, Q7]>>,
70 [Q0, Q1, Q2, Q3, Q4, Q5, Q6, Q7]>>,
72 [Q0, Q1, Q2, Q3, Q4, Q5, Q6, Q7]>>,
75 [Q0, Q1, Q2, Q3, Q4, Q5, Q6, Q7]>>,
77 CCAssignToReg<[Q0, Q1, Q2, Q3, Q4, Q5, Q6, Q7]>>,
106 [Q0, Q1, Q2, Q3, Q4, Q5, Q6, Q7]>>,
108 [Q0, Q1, Q2, Q3, Q4, Q5, Q6, Q7]>>,
110 [Q0, Q1, Q2, Q3, Q4, Q5, Q6, Q7]>>,
113 [Q0, Q1, Q2, Q3, Q4, Q5, Q6, Q7]>>,
115 CCAssignToReg<[Q0, Q1, Q2, Q3, Q4, Q5, Q6, Q7]>>
[all …]
/external/libhevc/common/arm/
Dihevc_sao_edge_offset_class0.s190 VCLT.U8 Q0,Q13,Q14 @II vcltq_u8(pu1_cur_row, pu1_cur_row_tmp)
211 …VSUB.I8 Q10,Q0,Q15 @II sign_left = vreinterpretq_s8_u8(vsubq_u8(cmp_lt, cmp_g…
215 VCLT.U8 Q0,Q13,Q14 @II vcltq_u8(pu1_cur_row, pu1_cur_row_tmp)
217 …VSUB.I8 Q11,Q0,Q15 @II sign_right = vreinterpretq_s8_u8(vsubq_u8(cmp_lt, cmp_…
221 …VMOVL.U8 Q0,D26 @II pi2_tmp_cur_row.val[0] = vreinterpretq_s16_u16(vmovl_u…
245 …VADDW.S8 Q0,Q0,D30 @II pi2_tmp_cur_row.val[0] = vaddw_s8(pi2_tmp_cur_row.val[…
248 …VMAX.S16 Q0,Q0,Q2 @II pi2_tmp_cur_row.val[0] = vmaxq_s16(pi2_tmp_cur_row.val…
251 …VMIN.U16 Q0,Q0,Q3 @II pi2_tmp_cur_row.val[0] = vreinterpretq_s16_u16(vminq_u…
253 VMOVN.I16 D0,Q0 @II vmovn_s16(pi2_tmp_cur_row.val[0])
Dihevc_sao_edge_offset_class1.s115 VMOV.I8 Q0,#2 @const_2 = vdupq_n_s8(2)
168 VADD.I8 Q6,Q0,Q8 @edge_idx = vaddq_s8(const_2, sign_up)
180 VADD.I8 Q11,Q0,Q8 @II edge_idx = vaddq_s8(const_2, sign_up)
241 VADD.I8 Q11,Q0,Q8 @edge_idx = vaddq_s8(const_2, sign_up)
310 VADD.I8 Q6,Q0,Q8 @edge_idx = vaddq_s8(const_2, sign_up)
320 VADD.I8 Q11,Q0,Q8 @II edge_idx = vaddq_s8(const_2, sign_up)
360 VADD.I8 Q11,Q0,Q8 @edge_idx = vaddq_s8(const_2, sign_up)
Dihevc_sao_edge_offset_class1_chroma.s118 VMOV.I8 Q0,#2 @const_2 = vdupq_n_s8(2)
172 VADD.I8 Q6,Q0,Q8 @edge_idx = vaddq_s8(const_2, sign_up)
184 VADD.I8 Q11,Q0,Q8 @II edge_idx = vaddq_s8(const_2, sign_up)
253 VADD.I8 Q11,Q0,Q8 @edge_idx = vaddq_s8(const_2, sign_up)
327 VADD.I8 Q6,Q0,Q8 @edge_idx = vaddq_s8(const_2, sign_up)
339 VADD.I8 Q11,Q0,Q8 @II edge_idx = vaddq_s8(const_2, sign_up)
390 VADD.I8 Q11,Q0,Q8 @edge_idx = vaddq_s8(const_2, sign_up)
/external/llvm/lib/Target/ARM/
DARMCallingConv.td75 CCIfType<[v2f64], CCAssignToReg<[Q0, Q1, Q2, Q3]>>,
82 CCIfType<[f32], CCAssignToStackWithShadow<4, 4, [Q0, Q1, Q2, Q3]>>,
83 CCIfType<[f64], CCAssignToStackWithShadow<8, 4, [Q0, Q1, Q2, Q3]>>,
84 CCIfType<[v2f64], CCAssignToStackWithShadow<16, 4, [Q0, Q1, Q2, Q3]>>,
94 CCIfType<[v2f64], CCAssignToReg<[Q0, Q1, Q2, Q3]>>,
138 CCIfType<[f32], CCAssignToStackWithShadow<4, 4, [Q0, Q1, Q2, Q3]>>,
139 CCIfType<[f64], CCAssignToStackWithShadow<8, 8, [Q0, Q1, Q2, Q3]>>,
141 CCAssignToStackWithShadow<16, 16, [Q0, Q1, Q2, Q3]>>>,
142 CCIfType<[v2f64], CCAssignToStackWithShadow<16, 8, [Q0, Q1, Q2, Q3]>>
215 CCIfType<[v2f64], CCAssignToReg<[Q0, Q1, Q2, Q3]>>,
[all …]
/external/swiftshader/third_party/LLVM/test/CodeGen/ARM/
D2010-06-29-PartialRedefFastAlloc.ll10 ; %reg1028 gets allocated %Q0, and if %reg1030 is reloaded for the partial
11 ; redef, it cannot also get %Q0.
/external/swiftshader/third_party/LLVM/lib/Target/ARM/
DARMCallingConv.td66 CCIfType<[v2f64], CCAssignToReg<[Q0, Q1, Q2, Q3]>>,
78 CCIfType<[v2f64], CCAssignToReg<[Q0, Q1, Q2, Q3]>>,
166 CCIfType<[v2f64], CCAssignToReg<[Q0, Q1, Q2, Q3]>>,
178 CCIfType<[v2f64], CCAssignToReg<[Q0, Q1, Q2, Q3]>>,
/external/libavc/common/arm/
Dih264_iquant_itrans_recon_a9.s147 vmull.s16 q0, d16, d20 @ Q0 = p[i] = (x[i] * trns_coeff[i]) where i = 0..3
152 vshl.s32 q0, q0, q15 @ Q0 = q[i] = (p[i] << (qP/6)) where i = 0..3
320 vmull.s16 q0, d16, d20 @ Q0 = p[i] = (x[i] * trns_coeff[i]) where i = 0..3
325 vshl.s32 q0, q0, q15 @ Q0 = q[i] = (p[i] << (qP/6)) where i = 0..3
508 vmull.s16 q0, d16, d20 @ Q0 = p[i] = (x[i] * trns_coeff[i]) where i = 0..3
515 vshl.s32 q0, q0, q15 @ Q0 = q[i] = (p[i] << (qP/6)) where i = 0..3
601 vswp d1, d8 @ Q0/Q1 = Row order x0/x1
625 vadd.s16 q0, q8, q2 @ Q0 = z0
697 vadd.s16 q0, q0, q11 @ Q0 = x0
717 vswp d1, d8 @ Q0/Q1 = Row order x0/x1
[all …]
/external/llvm/test/CodeGen/AArch64/
Darm64-return-vector.ll3 ; 2x64 vector should be returned in Q0.
/external/libxaac/decoder/
Dixheaacd_constants.h26 #define Q0 1 macro

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