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Searched refs:R10 (Results 1 – 25 of 147) sorted by relevance

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/external/libxaac/decoder/armv7/
Dixheaacd_rescale_subbandsamples.s38 LDR R10, [R9], #4
55 ADD R10, R10, R2, LSL #2
59 LDR R11, [R10]
61 LDRGE R5, [R10, #4]
64 STR R11, [R10], #4
67 STRGE R5, [R10], #4
71 LDR R10, [R9], #4
81 ADD R10, R10, R2, LSL #2
84 LDR R11, [R10]
86 LDRGE R5, [R10, #4]
[all …]
Dixheaacd_apply_rot.s38 ADD R10, R7, R8
39 STRH R10, [R11, #-96]
48 ADD R10, R7, R8
49 STRH R10, [R11], #4
57 ADD R10, R7, R8
58 STRH R10, [R11, #-96]
68 ADD R10, R7, R8
69 STRH R10, [R11], #4
86 SMULWB R10, R6, R8
89 QADD R5, R9, R10
[all …]
Dixheaacd_tns_parcor2lpc_32x16.s43 MOV R10, R9, ASR R8
48 MOV R11, R10
55 QADD R14, R10, R5
60 QADD R10, R10, R2
62 MOVS R2, R10
99 QADD R2, R10, R5
104 MOV R10, #0
111 SUBS R10, R6, #1
Dixheaacd_sbr_qmfanal32_winadds_eld.s64 MOV R10, R2 @
76 SUB R10, R10, #8
105 MOV R2, R10 @
107 MOV R10, R3
116 SUB R10, R10, #8
137 MOV R3, R10
149 MOV R10, R2
167 SUB R10, R10, #8
194 MOV R2, R10
203 MOV R10, R3
[all …]
Dixheaacd_overlap_add2.s47 ADD R10, R0, R9
49 VLD2.16 {D0, D1}, [R10]!
65 VLD2.16 {D8, D9}, [R10]!
79 VLD2.16 {D0, D1}, [R10]!
100 VLD2.16 {D8, D9}, [R10]!
134 MOV R10, R5, LSL #1
147 SUB R11, R10, #1
148 MOV R10, R11, LSL #2
149 ADD R10, R0, R10
151 SUB R10, R10, R12
[all …]
Dixheaacd_post_twiddle_overlap.s62 LDR R10, [R2], #4
64 SMULWT R11, R8, R10
65 SMULWB R12, R9, R10
66 SMULWB R5, R8, R10
67 SMLAWT R7, R9, R10, R5
74 SMULWB R10, R5, R9
77 ADD R8, R8, R10
81 LDR R10, [R6], #-32
84 SMULWB R7, R8, R10
87 SMULWT R12, R8, R10
[all …]
Dixheaacd_sbr_qmfsyn64_winadd.s41 MOV R10, R0
82 MOV R0, R10
89 MOV R10, R1
121 MOV R1, R10
123 MOV R10, R0
152 MOV R0, R10
158 MOV R10, R1
179 MOV R1, R10
196 MOV R10, R0
244 MOV R0, R10
[all …]
Dixheaacd_cos_sin_mod.s51 SUB R10, SP, #516
54 AND R12, R10, #7
56 ADDNE R10, R10, #4
72 ADD R11, R10, R6
106 STR R12, [R10, #4]
107 STR R14, [R10], #8
122 STR R12, [R10, #0xF8]
123 STR R14, [R10, #0xFC]
168 STR R12, [R10, #4]
169 STR R14, [R10], #8
[all …]
Dixheaacd_esbr_cos_sin_mod_loop2.s33 ADD R10, R0, #256
34 ADD R11, R10, R2, LSL #3
57 LDR R6, [R10]
64 LDR R6, [R10, #4]
66 STR R6, [R10], #4
90 VST1.32 {D12[1]}, [R10]!
96 VLD1.32 {D3}, [R10]
119 VST1.32 {D16[1]}, [R10]!
149 VST1.32 {D12[1]}, [R10]!
Dixheaacd_esbr_qmfsyn64_winadd.s30 MOV R10, R0
78 MOV R0, R10
83 MOV R10, R1
131 MOV R1, R10
133 MOV R10, R0
171 MOV R0, R10
176 MOV R10, R1
221 MOV R1, R10
223 MOV R10, R0
260 MOV R0, R10
[all …]
Dixheaacd_sbr_qmfanal32_winadds.s87 MOV R10, R2
127 MOV R2, R10
129 MOV R10, R3
157 MOV R3, R10
169 MOV R10, R2
213 MOV R2, R10
222 MOV R10, R3
249 MOV R3, R10
Dixheaacd_overlap_add1.s35 MOV R10, R5, LSL #1
36 SUB R11, R10, #1
37 MOV R10, R11, LSL #2
38 ADD R10, R0, R10
39 SUB R10, R10, #12
47 VLD1.32 {D6, D7}, [R10], R12
96 VLD1.32 {D6, D7}, [R10], R12
140 VLD1.32 {D6, D7}, [R10], R12
210 VLD1.32 {D6, D7}, [R10], R12
Dixheaacd_conv_ergtoamplitude.s32 LDR R10, =0x5A82
55 SMULWBNE R12, R12, R10
82 SMULWBNE R8, R8, R10
110 SMULWBNE R8, R8, R10
Dixheaacd_conv_ergtoamplitudelp.s32 LDR R10, =0x1FF
48 AND R6, R6, R10
74 AND R6, R6, R10
102 ANDS R6, R6, R10
/external/boringssl/src/ssl/test/runner/curve25519/
Dladderstep_amd64.s22 MOVQ DX,R10
27 ADDQ ·_2P1234(SB),R10
37 SUBQ 88(DI),R10
47 MOVQ R10,48(SP)
63 MOVQ AX,R10
77 ADDQ AX,R10
116 ADDQ AX,R10
129 SHLQ $13,R11:R10
130 ANDQ DX,R10
131 ADDQ R9,R10
[all …]
Dmul_amd64.s37 MOVQ AX,R10
53 ADDQ AX,R10
92 ADDQ AX,R10
104 ADDQ AX,R10
116 ADDQ AX,R10
129 SHLQ $13,R11:R10
130 ANDQ SI,R10
131 ADDQ R9,R10
145 ADDQ R10,DX
158 MOVQ DX,R10
[all …]
Dsquare_amd64.s25 MOVQ DX,R10
73 ADCQ DX,R10
78 ADCQ DX,R10
92 SHLQ $13,R10:R9
97 ADDQ R10,R11
122 MOVQ DX,R10
126 ANDQ SI,R10
131 MOVQ R10,32(DI)
Dfreeze_amd64.s22 MOVQ AX,R10
23 SUBQ $18,R10
50 CMPQ R10,SI
62 ANDQ R12,R10
63 SUBQ R10,SI
/external/swiftshader/third_party/LLVM/test/CodeGen/Mips/
Datomic.ll89 ; CHECK: ll $[[R10:[0-9]+]], 0($[[R2]])
90 ; CHECK: addu $[[R11:[0-9]+]], $[[R10]], $[[R9]]
92 ; CHECK: and $[[R13:[0-9]+]], $[[R10]], $[[R7]]
97 ; CHECK: and $[[R15:[0-9]+]], $[[R10]], $[[R6]]
120 ; CHECK: ll $[[R10:[0-9]+]], 0($[[R2]])
121 ; CHECK: subu $[[R11:[0-9]+]], $[[R10]], $[[R9]]
123 ; CHECK: and $[[R13:[0-9]+]], $[[R10]], $[[R7]]
128 ; CHECK: and $[[R15:[0-9]+]], $[[R10]], $[[R6]]
151 ; CHECK: ll $[[R10:[0-9]+]], 0($[[R2]])
152 ; CHECK: and $[[R18:[0-9]+]], $[[R10]], $[[R9]]
[all …]
/external/libhevc/decoder/arm/
Dihevcd_fmt_conv_420sp_to_rgba8888.s117 MOVW R10,#0x3311
118 VMOV.16 D0[0],R10 @//C1
120 MOVW R10,#0xF379
121 VMOV.16 D0[1],R10 @//C2
123 MOVW R10,#0xE5F8
124 VMOV.16 D0[2],R10 @//C3
126 MOVW R10,#0x4092
127 VMOV.16 D0[3],R10 @//C4
130 MOV R10,#128
131 VDUP.8 D1,R10
[all …]
/external/boringssl/src/ssl/test/runner/poly1305/
Dsum_amd64.s74 XORQ R10, R10 // h2
80 POLY1305_ADD(SI, R8, R9, R10)
83 POLY1305_MUL(R8, R9, R10, R11, R12, BX, CX, R13, R14)
107 ADCQ $0, R10
116 SBBQ $3, R10
/external/llvm/test/CodeGen/Mips/
Datomic.ll145 ; O0: ld $[[R10:[0-9]+]]
146 ; O0-NEXT: ll $[[R11:[0-9]+]], 0($[[R10]])
190 ; O0: ld $[[R10:[0-9]+]]
191 ; O0-NEXT: ll $[[R11:[0-9]+]], 0($[[R10]])
235 ; O0: ld $[[R10:[0-9]+]]
236 ; O0-NEXT: ll $[[R11:[0-9]+]], 0($[[R10]])
281 ; ALL: ll $[[R10:[0-9]+]], 0($[[R2]])
283 ; ALL: and $[[R13:[0-9]+]], $[[R10]], $[[R8]]
290 ; ALL: and $[[R15:[0-9]+]], $[[R10]], $[[R7]]
321 ; ALL: sllv $[[R10:[0-9]+]], $[[R9]], $[[R5]]
[all …]
/external/llvm/lib/Target/MSP430/
DMSP430RegisterInfo.cpp44 MSP430::R8, MSP430::R9, MSP430::R10, MSP430::R11, in getCalleeSavedRegs()
49 MSP430::R8, MSP430::R9, MSP430::R10, MSP430::R11, in getCalleeSavedRegs()
54 MSP430::R8, MSP430::R9, MSP430::R10, MSP430::R11, in getCalleeSavedRegs()
60 MSP430::R8, MSP430::R9, MSP430::R10, MSP430::R11, in getCalleeSavedRegs()
/external/llvm/lib/Target/XCore/
DXCoreRegisterInfo.td36 def R10 : Ri<10, "r10">, DwarfRegNum<[10]>;
49 R4, R5, R6, R7, R8, R9, R10,
56 R4, R5, R6, R7, R8, R9, R10,
/external/swiftshader/third_party/LLVM/lib/Target/ARM/
DARMBaseRegisterInfo.cpp74 ARM::LR, ARM::R11, ARM::R10, ARM::R9, ARM::R8, in getCalleeSavedRegs()
86 ARM::R11, ARM::R10, ARM::R8, in getCalleeSavedRegs()
429 ARM::R0, ARM::R2, ARM::R4, ARM::R6, ARM::R8, ARM::R10, in getRawAllocationOrder()
436 ARM::R8, ARM::R10 in getRawAllocationOrder()
441 ARM::R0, ARM::R2, ARM::R4, ARM::R8, ARM::R10, in getRawAllocationOrder()
448 ARM::R8, ARM::R10 in getRawAllocationOrder()
454 ARM::R1, ARM::R3, ARM::R10,ARM::R12,ARM::LR, ARM::R5, ARM::R7, in getRawAllocationOrder()
459 ARM::R0, ARM::R2, ARM::R10,ARM::R12,ARM::LR, ARM::R4, ARM::R7, in getRawAllocationOrder()
465 ARM::R0, ARM::R2, ARM::R4, ARM::R6, ARM::R10, in getRawAllocationOrder()
472 ARM::R10 in getRawAllocationOrder()
[all …]

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