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Searched refs:R13 (Results 1 – 25 of 91) sorted by relevance

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/external/boringssl/src/ssl/test/runner/poly1305/
Dsum_arm.s27 ADD $4, R13, R8
54 ADD $20, R13, R0
75 ADD $24, R13, R12
77 MOVW R0, 88(R13)
78 MOVW R1, 92(R13)
79 MOVW R2, 96(R13)
86 MOVW R6, 84(R13)
87 ADD $116, R13, g
96 ADD $100, R13, g
112 MOVW R14, 92(R13)
[all …]
Dsum_amd64.s83 POLY1305_MUL(R8, R9, R10, R11, R12, BX, CX, R13, R14)
93 XORQ R13, R13
99 MOVB -1(SI), R13
100 XORQ R13, BX
/external/boringssl/src/ssl/test/runner/curve25519/
Dladderstep_amd64.s25 MOVQ R9,R13
30 ADDQ ·_2P1234(SB),R13
40 SUBQ 112(DI),R13
50 MOVQ R13,72(SP)
69 MOVQ DX,R13
83 ADCQ DX,R13
122 ADCQ DX,R13
132 SHLQ $13,R13:R12
137 ADDQ R13,R14
184 MOVQ DX,R13
[all …]
Dsquare_amd64.s34 MOVQ AX,R13
48 ADDQ AX,R13
87 ADDQ AX,R13
98 SHLQ $13,R14:R13
99 ANDQ SI,R13
100 ADDQ R12,R13
116 ADDQ R13,DX
Dmul_amd64.s42 MOVQ DX,R13
58 ADCQ DX,R13
75 ADCQ DX,R13
109 ADCQ DX,R13
121 ADCQ DX,R13
132 SHLQ $13,R13:R12
137 ADDQ R13,R14
/external/swiftshader/third_party/LLVM/test/CodeGen/Mips/
Datomic.ll92 ; CHECK: and $[[R13:[0-9]+]], $[[R10]], $[[R7]]
93 ; CHECK: or $[[R14:[0-9]+]], $[[R13]], $[[R12]]
123 ; CHECK: and $[[R13:[0-9]+]], $[[R10]], $[[R7]]
124 ; CHECK: or $[[R14:[0-9]+]], $[[R13]], $[[R12]]
155 ; CHECK: and $[[R13:[0-9]+]], $[[R10]], $[[R7]]
156 ; CHECK: or $[[R14:[0-9]+]], $[[R13]], $[[R12]]
184 ; CHECK: and $[[R13:[0-9]+]], $[[R10]], $[[R7]]
185 ; CHECK: or $[[R14:[0-9]+]], $[[R13]], $[[R9]]
216 ; CHECK: and $[[R13:[0-9]+]], $[[R12]], $[[R6]]
217 ; CHECK: bne $[[R13]], $[[R9]], $[[BB1:[A-Z_0-9]+]]
[all …]
/external/llvm/test/CodeGen/Mips/
Datomic.ll150 ; ALL: addu $[[R13:[0-9]+]], $[[R12]], $[[R9]]
151 ; ALL: and $[[R14:[0-9]+]], $[[R13]], $[[R7]]
195 ; ALL: subu $[[R13:[0-9]+]], $[[R12]], $[[R9]]
196 ; ALL: and $[[R14:[0-9]+]], $[[R13]], $[[R7]]
240 ; ALL: and $[[R13:[0-9]+]], $[[R12]], $[[R9]]
241 ; ALL: nor $[[R14:[0-9]+]], $zero, $[[R13]]
283 ; ALL: and $[[R13:[0-9]+]], $[[R10]], $[[R8]]
284 ; ALL: or $[[R14:[0-9]+]], $[[R13]], $[[R18]]
326 ; ALL: ll $[[R13:[0-9]+]], 0($[[R2]])
327 ; ALL: and $[[R14:[0-9]+]], $[[R13]], $[[R7]]
[all …]
/external/llvm/lib/Target/MSP430/
DMSP430CallingConv.td19 // i16 are returned in registers R15, R14, R13, R12
20 CCIfType<[i16], CCAssignToReg<[R15, R14, R13, R12]>>
DMSP430RegisterInfo.td62 def R13 : MSP430RegWithSubregs<13, "r13", [R13B]>;
77 (add R12, R13, R14, R15, R11, R10, R9, R8, R7, R6, R5,
DMSP430RegisterInfo.cpp55 MSP430::R12, MSP430::R13, MSP430::R14, MSP430::R15, in getCalleeSavedRegs()
61 MSP430::R12, MSP430::R13, MSP430::R14, MSP430::R15, in getCalleeSavedRegs()
/external/swiftshader/third_party/LLVM/lib/Target/X86/
DX86RegisterInfo.cpp84 case X86::EDX: case X86::R13: return 3; in getCompactUnwindRegNum()
102 case X86::R13: case X86::R13D: case X86::R13W: case X86::R13B: in getSEHRegNum()
361 X86::RBX, X86::R12, X86::R13, X86::R14, X86::R15, X86::RBP, 0 in getCalleeSavedRegs()
366 X86::R13, X86::R14, X86::R15, X86::RBP, 0 in getCalleeSavedRegs()
371 X86::R12, X86::R13, X86::R14, X86::R15, in getCalleeSavedRegs()
433 X86::R12, X86::R13, X86::R14, X86::R15 in getReservedRegs()
707 case X86::R13B: case X86::R13W: case X86::R13D: case X86::R13: in getX86SubSuperRegister()
744 case X86::R13B: case X86::R13W: case X86::R13D: case X86::R13: in getX86SubSuperRegister()
780 case X86::R13B: case X86::R13W: case X86::R13D: case X86::R13: in getX86SubSuperRegister()
816 case X86::R13B: case X86::R13W: case X86::R13D: case X86::R13: in getX86SubSuperRegister()
[all …]
/external/libunwind/src/x86_64/
Dinit.h62 c->dwarf.loc[R13] = REG_INIT_LOC(c, r13, R13); in common_init()
DGget_save_loc.c44 case UNW_X86_64_R13: loc = c->dwarf.loc[R13]; break; in unw_get_save_loc()
Dunwind_i.h52 #define R13 13 macro
/external/llvm/lib/Target/X86/MCTargetDesc/
DX86MCTargetDesc.cpp110 X86::R8, X86::R9, X86::R10, X86::R11, X86::R12, X86::R13, in initLLVMToSEHAndCVRegMapping()
331 case X86::R13B: case X86::R13W: case X86::R13D: case X86::R13: in getX86SubSuperRegisterOrZero()
368 case X86::R13B: case X86::R13W: case X86::R13D: case X86::R13: in getX86SubSuperRegisterOrZero()
404 case X86::R13B: case X86::R13W: case X86::R13D: case X86::R13: in getX86SubSuperRegisterOrZero()
440 case X86::R13B: case X86::R13W: case X86::R13D: case X86::R13: in getX86SubSuperRegisterOrZero()
441 return X86::R13; in getX86SubSuperRegisterOrZero()
/external/llvm/lib/Target/AVR/
DAVRRegisterInfo.td58 def R13 : AVRReg<13, "r13">, DwarfRegNum<[13]>;
100 def R13R12 : AVRReg<12, "r13:r12", [R12, R13]>, DwarfRegNum<[12]>;
123 R28, R29, R17, R16, R15, R14, R13, R12, R11, R10,
130 add R15, R14, R13, R12, R11, R10, R9, R8, R7, R6, R5, R4, R3, R2, R0, R1
/external/swiftshader/third_party/LLVM/lib/Target/MBlaze/MCTargetDesc/
DMBlazeBaseInfo.h118 case MBlaze::R13 : return 13; in getMBlazeRegisterNumbering()
183 case 13 : return MBlaze::R13; in getMBlazeRegisterFromNumbering()
/external/swiftshader/third_party/LLVM/lib/Target/CellSPU/
DSPUCallingConv.td26 R12, R13, R14, R15, R16, R17, R18, R19, R20,
43 R12, R13, R14, R15, R16, R17, R18, R19, R20,
/external/strace/linux/x86_64/
Duserent.h3 XLAT(8*R13),
/external/llvm/test/MC/Hexagon/
Ddcfetch.s12 R13:12 = VALIGNB(R11:10,R9:8,P2)
/external/kernel-headers/original/uapi/asm-x86/asm/
Dptrace-abi.h35 #define R13 16 macro
/external/llvm/lib/Target/Lanai/MCTargetDesc/
DLanaiBaseInfo.h75 case Lanai::R13: in getLanaiRegisterNumbering()
/external/valgrind/coregrind/m_sigframe/
Dsigframe-amd64-darwin.c98 SC2(__r13,R13); in synthesize_ucontext()
126 SC2(R13,__r13); in restore_from_ucontext()
/external/swiftshader/third_party/LLVM/lib/Target/Alpha/
DAlphaRegisterInfo.td51 def R13 : GPR<13, "$13">, DwarfRegNum<[13]>;
122 R9, R10, R11, R12, R13, R14,
/external/swiftshader/third_party/LLVM/lib/Target/MSP430/
DMSP430CallingConv.td19 // i16 are returned in registers R15, R14, R13, R12

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