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Searched refs:R14 (Results 1 – 25 of 114) sorted by relevance

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/external/libxaac/decoder/armv7/
Dixheaacd_apply_rot.s27 STMFD SP!, {R4-R12, R14}
87 SMULWT R14, R5, R7
93 QADD R14, R14, R6
95 MOV R14, R14, LSL #2
96 STR R14, [R12, #0x7c]
103 SMULWT R14, R5, R7
110 QADD R14, R14, R6
112 MOV R14, R14, LSL #2
113 STR R14, [R12, #0xbc]
121 LDRSH R14, [R0, R11]
[all …]
Dixheaacd_cos_sin_mod.s40 STMFD SP!, {R4-R12, R14}
95 SMULWT R14, R0, R2
102 SMLAWB R14, R1, R2, R14
107 STR R14, [R10], #8
111 SMULWT R14, R1, R2
117 SMLAWB R14, R0, R2, R14
123 STR R14, [R10, #0xFC]
141 SMULWB R14, R1, R2
146 QSUB R14, R14, R6
154 STR R14, [R11, #0x104]
[all …]
Dixheaacd_tns_parcor2lpc_32x16.s26 STMFD SP!, {R2, R4-R12, R14}
50 LDRSH R14, [R0], #2
54 SMULBB R2, R2, R14
55 QADD R14, R10, R5
57 MOV R14, R14, ASR #16
61 STRH R14, [R4, #62]
69 @ LDRGTSH R14, [R0], #2
71 LDRSHGT R14, [R0], #2
77 LDRSH R14, [R0, #-2]!
79 SMULBB R2, R2, R14
[all …]
Dixheaacd_enery_calc_per_subband.s94 RSBS R14, R6, R10
104 MOV R4, R4, ASR R14
106 MOV R12, R12, ASR R14
113 RSB R12, R14, #0
127 SUB R14, R14, #23
137 ADD R12, R12, R14, LSL#1
Dixheaacd_conv_ergtoamplitude.s31 LDR R14, =0x1FF
48 ANDS R11, R11, R14
75 ANDS R11, R11, R14
103 ANDS R11, R11, R14
Dixheaacd_conv_ergtoamplitudelp.s38 MOV R14, #-16
54 MOV R14, R7, ASR #1
58 STRH R14, [R2, #2]
123 SUBS R6, R14, R1
Dixheaacd_tns_ar_filter_fixed.s111 MOV R14, #0
140 VDUP.32 Q1, R14 @Q1= accu = 0
176 VDUP.32 Q1, R14 @Q1= accu = 0
219 VDUP.32 Q1, R14 @Q1= accu = 0
263 VDUP.32 Q1, R14 @Q1= accu = 0
309 VDUP.32 Q1, R14 @Q1= accu = 0
397 MOV R14, #0
428 VDUP.32 Q1, R14 @Q1= accu = 0
465 VDUP.32 Q1, R14 @Q1= accu = 0
510 VDUP.32 Q1, R14 @Q1= accu = 0
/external/boringssl/src/ssl/test/runner/poly1305/
Dsum_arm.s76 MOVM.IB [R4-R8, R14], (R12)
80 MOVW R1, R14
97 MOVW_UNALIGNED(R14, g, R0, 0)
98 MOVW_UNALIGNED(R14, g, R0, 4)
99 MOVW_UNALIGNED(R14, g, R0, 8)
100 MOVW_UNALIGNED(R14, g, R0, 12)
102 ADD $16, R14
106 MOVM.IA.W (R14), [R0-R3]
112 MOVW R14, 92(R13)
126 ADD $116, R13, R14
[all …]
/external/boringssl/src/ssl/test/runner/curve25519/
Dladderstep_amd64.s73 MOVQ AX,R14
87 ADDQ AX,R14
96 ADDQ AX,R14
135 SHLQ $13,R15:R14
136 ANDQ DX,R14
137 ADDQ R13,R14
154 ADDQ R14,CX
188 MOVQ AX,R14
202 ADDQ AX,R14
211 ADDQ AX,R14
[all …]
Dmul_amd64.s45 MOVQ AX,R14
61 ADDQ AX,R14
78 ADDQ AX,R14
96 ADDQ AX,R14
124 ADDQ AX,R14
135 SHLQ $13,R15:R14
136 ANDQ SI,R14
137 ADDQ R13,R14
153 ADDQ R14,DX
Dsquare_amd64.s35 MOVQ DX,R14
49 ADCQ DX,R14
88 ADCQ DX,R14
98 SHLQ $13,R14:R13
103 ADDQ R14,R15
/external/swiftshader/third_party/LLVM/test/CodeGen/Mips/
Datomic.ll93 ; CHECK: or $[[R14:[0-9]+]], $[[R13]], $[[R12]]
94 ; CHECK: sc $[[R14]], 0($[[R2]])
95 ; CHECK: beq $[[R14]], $zero, $[[BB0]]
124 ; CHECK: or $[[R14:[0-9]+]], $[[R13]], $[[R12]]
125 ; CHECK: sc $[[R14]], 0($[[R2]])
126 ; CHECK: beq $[[R14]], $zero, $[[BB0]]
156 ; CHECK: or $[[R14:[0-9]+]], $[[R13]], $[[R12]]
157 ; CHECK: sc $[[R14]], 0($[[R2]])
158 ; CHECK: beq $[[R14]], $zero, $[[BB0]]
185 ; CHECK: or $[[R14:[0-9]+]], $[[R13]], $[[R9]]
[all …]
/external/llvm/test/CodeGen/Mips/
Datomic.ll151 ; ALL: and $[[R14:[0-9]+]], $[[R13]], $[[R7]]
153 ; ALL: or $[[R16:[0-9]+]], $[[R15]], $[[R14]]
196 ; ALL: and $[[R14:[0-9]+]], $[[R13]], $[[R7]]
198 ; ALL: or $[[R16:[0-9]+]], $[[R15]], $[[R14]]
241 ; ALL: nor $[[R14:[0-9]+]], $zero, $[[R13]]
242 ; ALL: and $[[R15:[0-9]+]], $[[R14]], $[[R7]]
284 ; ALL: or $[[R14:[0-9]+]], $[[R13]], $[[R18]]
285 ; ALL: sc $[[R14]], 0($[[R2]])
286 ; NOT-MICROMIPS: beqz $[[R14]], $[[BB0]]
287 ; MICROMIPS: beqzc $[[R14]], $[[BB0]]
[all …]
/external/llvm/lib/Target/MSP430/
DMSP430CallingConv.td19 // i16 are returned in registers R15, R14, R13, R12
20 CCIfType<[i16], CCAssignToReg<[R15, R14, R13, R12]>>
DMSP430RegisterInfo.td63 def R14 : MSP430RegWithSubregs<14, "r14", [R14B]>;
77 (add R12, R13, R14, R15, R11, R10, R9, R8, R7, R6, R5,
DMSP430RegisterInfo.cpp55 MSP430::R12, MSP430::R13, MSP430::R14, MSP430::R15, in getCalleeSavedRegs()
61 MSP430::R12, MSP430::R13, MSP430::R14, MSP430::R15, in getCalleeSavedRegs()
/external/swiftshader/third_party/LLVM/lib/Target/X86/
DX86RegisterInfo.cpp85 case X86::EDI: case X86::R14: return 4; in getCompactUnwindRegNum()
103 case X86::R14: case X86::R14D: case X86::R14W: case X86::R14B: in getSEHRegNum()
361 X86::RBX, X86::R12, X86::R13, X86::R14, X86::R15, X86::RBP, 0 in getCalleeSavedRegs()
366 X86::R13, X86::R14, X86::R15, X86::RBP, 0 in getCalleeSavedRegs()
371 X86::R12, X86::R13, X86::R14, X86::R15, in getCalleeSavedRegs()
433 X86::R12, X86::R13, X86::R14, X86::R15 in getReservedRegs()
709 case X86::R14B: case X86::R14W: case X86::R14D: case X86::R14: in getX86SubSuperRegister()
746 case X86::R14B: case X86::R14W: case X86::R14D: case X86::R14: in getX86SubSuperRegister()
782 case X86::R14B: case X86::R14W: case X86::R14D: case X86::R14: in getX86SubSuperRegister()
818 case X86::R14B: case X86::R14W: case X86::R14D: case X86::R14: in getX86SubSuperRegister()
[all …]
/external/llvm/test/CodeGen/Hexagon/
Dpic-regusage.ll3 ; Force the use of R14 (by clobbering everything else in the inline asm).
4 ; Make sure that R14 is not set before the __save call (which will clobber
5 ; R14, R15 and R28).
/external/libunwind/src/x86_64/
Dinit.h63 c->dwarf.loc[R14] = REG_INIT_LOC(c, r14, R14); in common_init()
/external/llvm/lib/Target/X86/MCTargetDesc/
DX86MCTargetDesc.cpp111 X86::R14, X86::R15, X86::R8B, X86::R9B, X86::R10B, X86::R11B, in initLLVMToSEHAndCVRegMapping()
333 case X86::R14B: case X86::R14W: case X86::R14D: case X86::R14: in getX86SubSuperRegisterOrZero()
370 case X86::R14B: case X86::R14W: case X86::R14D: case X86::R14: in getX86SubSuperRegisterOrZero()
406 case X86::R14B: case X86::R14W: case X86::R14D: case X86::R14: in getX86SubSuperRegisterOrZero()
442 case X86::R14B: case X86::R14W: case X86::R14D: case X86::R14: in getX86SubSuperRegisterOrZero()
443 return X86::R14; in getX86SubSuperRegisterOrZero()
/external/llvm/lib/Target/AVR/
DAVRRegisterInfo.td59 def R14 : AVRReg<14, "r14">, DwarfRegNum<[14]>;
99 def R15R14 : AVRReg<14, "r15:r14", [R14, R15]>, DwarfRegNum<[14]>;
123 R28, R29, R17, R16, R15, R14, R13, R12, R11, R10,
130 add R15, R14, R13, R12, R11, R10, R9, R8, R7, R6, R5, R4, R3, R2, R0, R1
/external/swiftshader/third_party/LLVM/lib/Target/MBlaze/MCTargetDesc/
DMBlazeBaseInfo.h119 case MBlaze::R14 : return 14; in getMBlazeRegisterNumbering()
184 case 14 : return MBlaze::R14; in getMBlazeRegisterFromNumbering()
/external/swiftshader/third_party/LLVM/lib/Target/CellSPU/
DSPUCallingConv.td26 R12, R13, R14, R15, R16, R17, R18, R19, R20,
43 R12, R13, R14, R15, R16, R17, R18, R19, R20,
/external/swiftshader/third_party/LLVM/lib/Target/PowerPC/
DPPCFrameLowering.h171 {PPC::R14, -72}, in getCalleeSavedSpillSlots()
250 {PPC::R14, -140}, in getCalleeSavedSpillSlots()
/external/strace/linux/x86_64/
Duserent.h2 XLAT(8*R14),

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