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/external/libxaac/decoder/armv7/
Dixheaacd_apply_rot.s28 LDR R5, =0x59e
30 ADD R11, R0, R5
32 LDRSH R5, [R11, #-98]
36 ADD R9, R5, R6
42 LDRSH R5, [R11, #-2]
46 ADD R9, R5, R6
51 LDRSH R5, [R11, #-98]
55 ADD R9, R5, R6
62 LDRSH R5, [R11, #-2]
66 ADD R9, R5, R6
[all …]
Dixheaacd_cos_sin_mod.s42 LDR R5, [R1]
43 MOV R7, R5, ASR #1
45 MOV R5, R7, ASR #2
91 SUBS R5, R5, #1
219 LDR R5, [R1]
230 CMP R5, #64
231 LDR R5, [SP, #12]
244 STR R5, [SP, #-4]!
245 STR R5, [SP, #-4]!
246 STR R5, [SP, #-4]!
[all …]
Dixheaacd_rescale_subbandsamples.s28 LDR R5, [SP, #36]
34 SUBS R6, R6, R5
37 ADD R9, R0, R5, LSL#2
61 LDRGE R5, [R10, #4]
66 MOVGE R5, R5, LSL R4
67 STRGE R5, [R10], #4
86 LDRGE R5, [R10, #4]
91 MOVGE R5, R5, ASR R4
92 STRGE R5, [R10], #4
106 ADD R5, R1, R5, LSL#2
[all …]
Dixheaacd_post_twiddle_overlap.s32 LDR R5, [sp, #104]
46 RSB R9, R5, #15
48 VDUP.32 Q8, R5
49 SUB R5, R5, #16
50 STR R5, [sp, #116]
66 SMULWB R5, R8, R10
67 SMLAWT R7, R9, R10, R5
69 MVN R5, R7
70 ADD R5, R5, #1
74 SMULWB R10, R5, R9
[all …]
Dixheaacd_sbr_qmfsyn64_winadd.s31 LDR R5, [SP, #108]
60 MOV R5, R5, LSL #1
186 VST1.16 D28[0], [R3], R5
193 VST1.16 D28[1], [R3], R5
201 VST1.16 D28[2], [R3], R5
204 VST1.16 D28[3], [R3], R5
274 VST1.16 D28[0], [R3], R5
283 VST1.16 D28[1], [R3], R5
286 VST1.16 D28[2], [R3], R5
289 VST1.16 D28[3], [R3], R5
[all …]
Dixheaacd_dec_DCT2_64_asm.s77 ADD R5, R0, #252
82 SUB R5, R5, #28
87 VLD2.32 {Q2, Q3}, [R5]!
111 SUB R12, R5, #32
116 SUB R5, R5, #64
118 VLD2.32 {Q2, Q3}, [R5]!
154 SUB R12, R5, #32
157 SUB R5, R5, #64
162 VLD2.32 {Q2, Q3}, [R5]!
209 SUB R12, R5, #32
[all …]
Dixheaacd_esbr_fwd_modulation.s32 ADD R5, R0, R4, LSL #3
37 SUB R5, R5, #32
39 VLD1.32 {D4, D5, D6, D7}, [R5]
66 ldr R5, =0x41FC
67 ADD R2, R4, R5
76 LDRSH R5, [R3, #0x2A]
78 SUB R4, R4, R5
Dixheaacd_esbr_qmfsyn64_winadd.s11 @R5->ch_fac
21 LDR R5, [SP, #104]
47 MOV R5, R5, LSL #2
118 VST1.32 D26[0], [R3], R5
119 VST1.32 D26[1], [R3], R5
123 VST1.32 D27[0], [R3], R5
124 VST1.32 D27[1], [R3], R5
211 VST1.32 D26[0], [R3], R5
212 VST1.32 D26[1], [R3], R5
216 VST1.32 D27[0], [R3], R5
[all …]
Dixheaacd_enery_calc_per_subband.s31 MOV R5, R3
41 SUBS R5, R5, R4
145 SUBS R5, R5, #1
152 SUBS R5, R5, #1
Dixheaacd_no_lap1.s29 MOV R5, #448
30 SUB R6, R5, #1
49 SUB R5, R5, #8
68 SUBS R5, R5, #8
Dixheaacd_tns_parcor2lpc_32x16.s30 MOV R5, #0x8000
55 QADD R14, R10, R5
86 QADD R14, R9, R5
98 QADD R11, R11, R5
99 QADD R2, R10, R5
Dixheaacd_mps_synt_out_calc.s19 ADD R5, R2, R7, LSL #2
26 VLD1.32 {D2, D3}, [R5]!
48 ADD R5, R5, R7, LSL #2
Dixheaacd_overlap_add2.s32 LDR R5, [SP, #108]
43 MOV R8, R5
44 SUB R12, R5, #1
45 MOV R9, R5, LSL #2
133 SMULBB R7, R5, R6
134 MOV R10, R5, LSL #1
197 SUB R5, R5, #8
239 SUBS R5, R5, #8
Dixheaacd_dct3_32.s58 SUB R5, R7, #112
71 VLD1.32 {Q4}, [R5], R12
110 SUB R5, R7, #112
116 VLD1.32 {Q4}, [R5], R12
144 SUB R5, R7, #124
149 VLD1.32 {Q4}, [R5], R11
190 SUB R5, R7, #116
198 VLD1.32 D8[0], [R5], R11
205 VLD1.32 D8[1], [R5], R11
210 VLD1.32 D9[0], [R5], R11
[all …]
/external/llvm/test/CodeGen/Mips/llvm-ir/
Dmul.ll4 ; RUN: FileCheck %s -check-prefixes=ALL,32R1-R5,GP32
6 ; RUN: FileCheck %s -check-prefixes=ALL,32R1-R5,32R2-R5,GP32
8 ; RUN: FileCheck %s -check-prefixes=ALL,32R1-R5,32R2-R5,GP32
10 ; RUN: FileCheck %s -check-prefixes=ALL,32R1-R5,32R2-R5,GP32
16 ; RUN: FileCheck %s -check-prefixes=ALL,64R1-R5,GP64-NOT-R6
18 ; RUN: FileCheck %s -check-prefixes=ALL,64R1-R5,GP64,GP64-NOT-R6
20 ; RUN: FileCheck %s -check-prefixes=ALL,64R1-R5,GP64,GP64-NOT-R6
22 ; RUN: FileCheck %s -check-prefixes=ALL,64R1-R5,GP64,GP64-NOT-R6
41 ; 32R1-R5: mul $[[T0:[0-9]+]], $4, $5
42 ; 32R1-R5: sll $[[T0]], $[[T0]], 31
[all …]
Durem.ll6 ; RUN: -check-prefixes=ALL,GP32,R2-R5,R2-R6,NOT-R6
8 ; RUN: -check-prefixes=ALL,GP32,R2-R5,R2-R6,NOT-R6
10 ; RUN: -check-prefixes=ALL,GP32,R2-R5,R2-R6,NOT-R6
21 ; RUN: -check-prefixes=ALL,R2-R5,R2-R6,GP64-NOT-R6,NOT-R6
23 ; RUN: -check-prefixes=ALL,R2-R5,R2-R6,GP64-NOT-R6,NOT-R6
25 ; RUN: -check-prefixes=ALL,R2-R5,R2-R6,GP64-NOT-R6,NOT-R6
86 ; R2-R5: andi $[[T0:[0-9]+]], $5, 255
87 ; R2-R5: andi $[[T1:[0-9]+]], $4, 255
88 ; R2-R5: divu $zero, $[[T1]], $[[T0]]
89 ; R2-R5: teq $[[T0]], $zero, 7
[all …]
Dsrem.ll6 ; RUN: -check-prefixes=ALL,GP32,R2-R5,R2-R6,NOT-R6
8 ; RUN: -check-prefixes=ALL,GP32,R2-R5,R2-R6,NOT-R6
10 ; RUN: -check-prefixes=ALL,GP32,R2-R5,R2-R6,NOT-R6
21 ; RUN: -check-prefixes=ALL,R2-R5,R2-R6,GP64-NOT-R6,NOT-R6
23 ; RUN: -check-prefixes=ALL,R2-R5,R2-R6,GP64-NOT-R6,NOT-R6
25 ; RUN: -check-prefixes=ALL,R2-R5,R2-R6,GP64-NOT-R6,NOT-R6
76 ; R2-R5: div $zero, $4, $5
77 ; R2-R5: teq $5, $zero, 7
78 ; R2-R5: mfhi $[[T0:[0-9]+]]
79 ; R2-R5: seb $2, $[[T0]]
[all …]
Dashr.ll4 ; RUN: -check-prefixes=ALL,GP32,32R1-R5
6 ; RUN: -check-prefixes=ALL,GP32,32R1-R5
8 ; RUN: -check-prefixes=ALL,GP32,32R1-R5
10 ; RUN: -check-prefixes=ALL,GP32,32R1-R5
101 ; 32R1-R5: srlv $[[T0:[0-9]+]], $5, $7
102 ; 32R1-R5: not $[[T1:[0-9]+]], $7
103 ; 32R1-R5: sll $[[T2:[0-9]+]], $4, 1
104 ; 32R1-R5: sllv $[[T3:[0-9]+]], $[[T2]], $[[T1]]
105 ; 32R1-R5: or $3, $[[T3]], $[[T0]]
106 ; 32R1-R5: srav $[[T4:[0-9]+]], $4, $7
[all …]
Dsdiv.ll6 ; RUN: -check-prefixes=ALL,NOT-R6,R2-R5,GP32
8 ; RUN: -check-prefixes=ALL,NOT-R6,R2-R5,GP32
10 ; RUN: -check-prefixes=ALL,NOT-R6,R2-R5,GP32
21 ; RUN: -check-prefixes=ALL,NOT-R6,R2-R5,GP64-NOT-R6
23 ; RUN: -check-prefixes=ALL,NOT-R6,R2-R5,GP64-NOT-R6
25 ; RUN: -check-prefixes=ALL,NOT-R6,R2-R5,GP64-NOT-R6
79 ; R2-R5: div $zero, $4, $5
80 ; R2-R5: teq $5, $zero, 7
81 ; R2-R5: mflo $[[T0:[0-9]+]]
83 ; R2-R5: seb $2, $[[T0]]
[all …]
Dlshr.ll4 ; RUN: -check-prefixes=ALL,GP32,32R1-R5
6 ; RUN: -check-prefixes=ALL,GP32,32R1-R5
8 ; RUN: -check-prefixes=ALL,GP32,32R1-R5
10 ; RUN: -check-prefixes=ALL,GP32,32R1-R5
99 ; 32R1-R5: srlv $[[T0:[0-9]+]], $5, $7
100 ; 32R1-R5: not $[[T1:[0-9]+]], $7
101 ; 32R1-R5: sll $[[T2:[0-9]+]], $4, 1
102 ; 32R1-R5: sllv $[[T3:[0-9]+]], $[[T2]], $[[T1]]
103 ; 32R1-R5: or $3, $[[T3]], $[[T0]]
104 ; 32R1-R5: srlv $[[T4:[0-9]+]], $4, $7
[all …]
Dshl.ll4 ; RUN: -check-prefixes=ALL,GP32,NOT-R2-R6,32R1-R5
6 ; RUN: -check-prefixes=ALL,GP32,32R1-R5,R2-R6
8 ; RUN: -check-prefixes=ALL,GP32,32R1-R5,R2-R6
10 ; RUN: -check-prefixes=ALL,GP32,32R1-R5,R2-R6
115 ; 32R1-R5: sllv $[[T0:[0-9]+]], $4, $7
116 ; 32R1-R5: not $[[T1:[0-9]+]], $7
117 ; 32R1-R5: srl $[[T2:[0-9]+]], $5, 1
118 ; 32R1-R5: srlv $[[T3:[0-9]+]], $[[T2]], $[[T1]]
119 ; 32R1-R5: or $2, $[[T0]], $[[T3]]
120 ; 32R1-R5: sllv $[[T4:[0-9]+]], $5, $7
[all …]
/external/boringssl/src/ssl/test/runner/poly1305/
Dsum_arm.s29 MOVM.IA.W (R1), [R2-R5]
35 MOVW R5>>8, R12
38 ORR R5<<18, R11, R11
43 AND R11, R5, R5
49 EOR R5, R5, R5
52 MOVM.IA.W (R1), [R2-R5]
122 ADD R0, R5, R5
130 MULLU R4, R5, (R11, g)
131 MULLU R3, R5, (R14, R12)
146 MULLU R2, R5, (R11, g)
[all …]
/external/llvm/test/CodeGen/Mips/
Datomic.ll137 ; CHECK-EB: sll $[[R5:[0-9]+]], $[[R4]], 3
138 ; CHECK-EL: sll $[[R5:[0-9]+]], $[[R3]], 3
140 ; ALL: sllv $[[R7:[0-9]+]], $[[R6]], $[[R5]]
142 ; ALL: sllv $[[R9:[0-9]+]], $4, $[[R5]]
160 ; ALL: srlv $[[R18:[0-9]+]], $[[R17]], $[[R5]]
181 ; CHECK-EL: sll $[[R5:[0-9]+]], $[[R3]], 3
183 ; CHECK-EB: sll $[[R5:[0-9]+]], $[[R4]], 3
185 ; ALL: sllv $[[R7:[0-9]+]], $[[R6]], $[[R5]]
187 ; ALL: sllv $[[R9:[0-9]+]], $4, $[[R5]]
205 ; ALL: srlv $[[R18:[0-9]+]], $[[R17]], $[[R5]]
[all …]
Dcttz-v.ll14 ; MIPS32-DAG: addiu $[[R5:[0-9]+]], $5, -1
16 ; MIPS32-DAG: and $[[R7:[0-9]+]], $[[R6]], $[[R5]]
29 ; MIPS64-DAG: addiu $[[R5:[0-9]+]], $[[A1]], -1
31 ; MIPS64-DAG: and $[[R7:[0-9]+]], $[[R6]], $[[R5]]
/external/swiftshader/third_party/LLVM/test/CodeGen/Mips/
Datomic.ll83 ; CHECK: ori $[[R5:[0-9]+]], $zero, 255
84 ; CHECK: sllv $[[R6:[0-9]+]], $[[R5]], $[[R4]]
114 ; CHECK: ori $[[R5:[0-9]+]], $zero, 255
115 ; CHECK: sllv $[[R6:[0-9]+]], $[[R5]], $[[R4]]
145 ; CHECK: ori $[[R5:[0-9]+]], $zero, 255
146 ; CHECK: sllv $[[R6:[0-9]+]], $[[R5]], $[[R4]]
177 ; CHECK: ori $[[R5:[0-9]+]], $zero, 255
178 ; CHECK: sllv $[[R6:[0-9]+]], $[[R5]], $[[R4]]
206 ; CHECK: ori $[[R5:[0-9]+]], $zero, 255
207 ; CHECK: sllv $[[R6:[0-9]+]], $[[R5]], $[[R4]]

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