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Searched refs:R600 (Results 1 – 25 of 101) sorted by relevance

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/external/llvm/test/CodeGen/AMDGPU/
Dfdiv.ll6 ; RUN: llc -march=r600 -mcpu=redwood < %s | FileCheck -check-prefix=R600 -check-prefix=FUNC %s
15 ; R600-DAG: RECIP_IEEE * T{{[0-9]+\.[XYZW]}}, KC0[2].W
16 ; R600-DAG: MUL_IEEE {{\** *}}T{{[0-9]+\.[XYZW]}}, KC0[2].Z, PS
38 ; R600-DAG: RECIP_IEEE * T{{[0-9]+\.[XYZW]}}, KC0[2].W
39 ; R600-DAG: MUL_IEEE {{\** *}}T{{[0-9]+\.[XYZW]}}, KC0[2].Z, PS
54 ; R600-DAG: RECIP_IEEE * T{{[0-9]+\.[XYZW]}}, KC0[2].W
55 ; R600-DAG: MUL_IEEE {{\** *}}T{{[0-9]+\.[XYZW]}}, KC0[2].Z, PS
70 ; R600-DAG: RECIP_IEEE * T{{[0-9]+\.[XYZW]}}, KC0[3].Z
71 ; R600-DAG: RECIP_IEEE * T{{[0-9]+\.[XYZW]}}, KC0[3].Y
72 ; R600-DAG: MUL_IEEE {{\** *}}T{{[0-9]+\.[XYZW]}}, KC0[3].X, PS
[all …]
Dsetcc.ll2 ; RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck --check-prefix=R600 --check-prefix=FUNC %s
7 ; R600-DAG: SETE_INT * T{{[0-9]+\.[XYZW]}}, KC0[3].X, KC0[3].Z
8 ; R600-DAG: SETE_INT * T{{[0-9]+\.[XYZW]}}, KC0[2].W, KC0[3].Y
18 ; R600-DAG: SETE_INT * T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
19 ; R600-DAG: SETE_INT * T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
20 ; R600-DAG: SETE_INT * T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
21 ; R600-DAG: SETE_INT * T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
38 ; R600: SETE_DX10
49 ; R600: SETGT_DX10
60 ; R600: SETGE_DX10
[all …]
Dfadd.ll3 ; RUN: llc -march=r600 -mcpu=redwood < %s | FileCheck %s -check-prefix=R600 -check-prefix=FUNC
6 ; R600: ADD {{\** *}}T{{[0-9]+\.[XYZW]}}, KC0[2].Z, KC0[2].W
15 ; R600-DAG: ADD {{\** *}}T{{[0-9]\.[XYZW]}}, KC0[3].X, KC0[3].Z
16 ; R600-DAG: ADD {{\** *}}T{{[0-9]\.[XYZW]}}, KC0[2].W, KC0[3].Y
26 ; R600: ADD {{\** *}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
27 ; R600: ADD {{\** *}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
28 ; R600: ADD {{\** *}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
29 ; R600: ADD {{\** *}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
44 ; R600: ADD
45 ; R600: ADD
[all …]
Dbuild_vector.ll1 ; RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck %s --check-prefix=R600
5 ; R600: {{^}}build_vector2:
6 ; R600: MOV
7 ; R600: MOV
8 ; R600-NOT: MOV
19 ; R600: {{^}}build_vector4:
20 ; R600: MOV
21 ; R600: MOV
22 ; R600: MOV
23 ; R600: MOV
[all …]
Duint_to_fp.ll3 ; RUN: llc -march=r600 -mcpu=redwood < %s | FileCheck -check-prefix=R600 -check-prefix=FUNC %s
8 ; R600: UINT_TO_FLT * T{{[0-9]+\.[XYZW]}}, KC0[2].Z
18 ; R600: INT_TO_FLT
33 ; R600-DAG: UINT_TO_FLT * T{{[0-9]+\.[XYZW]}}, KC0[2].W
34 ; R600-DAG: UINT_TO_FLT * T{{[0-9]+\.[XYZW]}}, KC0[3].X
48 ; R600: UINT_TO_FLT * T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
49 ; R600: UINT_TO_FLT * T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
50 ; R600: UINT_TO_FLT * T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
51 ; R600: UINT_TO_FLT * T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
65 ; R600: UINT_TO_FLT * T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
[all …]
Dload-global-f32.ll5 ; RUN: llc -march=r600 -mcpu=redwood < %s | FileCheck -check-prefix=R600 -check-prefix=FUNC %s
6 ; RUN: llc -march=r600 -mcpu=cayman < %s | FileCheck -check-prefix=R600 -check-prefix=FUNC %s
12 ; R600: VTX_READ_32 T{{[0-9]+}}.X, T{{[0-9]+}}.X, 0
24 ; R600: VTX_READ_64
36 ; R600: VTX_READ_128
48 ; R600: VTX_READ_128
62 ; R600: VTX_READ_128
63 ; R600: VTX_READ_128
82 ; R600: VTX_READ_128
83 ; R600: VTX_READ_128
[all …]
Dfneg.ll3 ; RUN: llc -march=r600 -mcpu=redwood < %s | FileCheck -check-prefix=R600 -check-prefix=FUNC %s
6 ; R600: -PV
16 ; R600: -PV
17 ; R600: -PV
28 ; R600: -PV
29 ; R600: -T
30 ; R600: -PV
31 ; R600: -PV
48 ; R600-NOT: XOR
49 ; R600: -KC0[2].Z
Dfabs.ll3 ; RUN: llc -march=r600 -mcpu=redwood < %s | FileCheck -check-prefix=R600 -check-prefix=FUNC %s
11 ; R600-NOT: AND
12 ; R600: |PV.{{[XYZW]}}|
24 ; R600-NOT: AND
25 ; R600: |PV.{{[XYZW]}}|
37 ; R600: |{{(PV|T[0-9])\.[XYZW]}}|
47 ; R600: |{{(PV|T[0-9])\.[XYZW]}}|
48 ; R600: |{{(PV|T[0-9])\.[XYZW]}}|
59 ; R600: |{{(PV|T[0-9])\.[XYZW]}}|
60 ; R600: |{{(PV|T[0-9])\.[XYZW]}}|
[all …]
Dllvm.rint.ll3 ; RUN: llc -march=r600 -mcpu=redwood < %s | FileCheck %s -check-prefix=R600 -check-prefix=FUNC
6 ; R600: RNDNE
17 ; R600: RNDNE
18 ; R600: RNDNE
30 ; R600: RNDNE
31 ; R600: RNDNE
32 ; R600: RNDNE
33 ; R600: RNDNE
Dllvm.round.ll3 ; RUN: llc -march=r600 -mcpu=redwood < %s | FileCheck -check-prefix=R600 -check-prefix=FUNC %s
17 ; R600: TRUNC {{.*}}, [[ARG:KC[0-9]\[[0-9]+\]\.[XYZW]]]
18 ; R600-DAG: ADD {{.*}},
19 ; R600-DAG: BFI_INT
20 ; R600-DAG: SETGE
21 ; R600-DAG: CNDE
22 ; R600-DAG: ADD
36 ; R600: CF_END
45 ; R600: CF_END
54 ; R600: CF_END
Dbfi_int.ll1 ; RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck --check-prefix=R600 %s
8 ; R600: {{^}}bfi_def:
9 ; R600: BFI_INT
24 ; R600: {{^}}bfi_sha256_ch:
25 ; R600: BFI_INT
39 ; R600: {{^}}bfi_sha256_ma:
40 ; R600: XOR_INT * [[DST:T[0-9]+\.[XYZW]]], KC0[2].Z, KC0[2].W
41 ; R600: BFI_INT * {{T[0-9]+\.[XYZW]}}, {{[[DST]]|PV\.[XYZW]}}, KC0[3].X, KC0[2].W
Drotr.ll1 ; RUN: llc -march=r600 -mcpu=redwood < %s | FileCheck --check-prefix=R600 -check-prefix=FUNC %s
6 ; R600: BIT_ALIGN_INT
20 ; R600: BIT_ALIGN_INT
21 ; R600: BIT_ALIGN_INT
36 ; R600: BIT_ALIGN_INT
37 ; R600: BIT_ALIGN_INT
38 ; R600: BIT_ALIGN_INT
39 ; R600: BIT_ALIGN_INT
Dsint_to_fp.ll3 ; RUN: llc -march=r600 -mcpu=redwood < %s | FileCheck -check-prefix=R600 -check-prefix=FUNC %s
8 ; R600: INT_TO_FLT * T{{[0-9]+\.[XYZW]}}, KC0[2].Z
18 ; R600: INT_TO_FLT
33 ; R600-DAG: INT_TO_FLT * T{{[0-9]+\.[XYZW]}}, KC0[2].W
34 ; R600-DAG: INT_TO_FLT * T{{[0-9]+\.[XYZW]}}, KC0[3].X
48 ; R600: INT_TO_FLT * T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
49 ; R600: INT_TO_FLT * T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
50 ; R600: INT_TO_FLT * T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
51 ; R600: INT_TO_FLT * T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
65 ; R600: INT_TO_FLT * T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
[all …]
Dfsqrt.ll3 ; RUN: llc -march=r600 -mcpu=redwood < %s | FileCheck -check-prefix=R600 -check-prefix=FUNC %s
30 ; R600: RECIPSQRT_CLAMPED * T{{[0-9]\.[XYZW]}}, KC0[2].Z
31 ; R600: MUL NON-IEEE T{{[0-9]\.[XYZW]}}, KC0[2].Z, PS
43 ; R600-DAG: RECIPSQRT_CLAMPED * T{{[0-9]\.[XYZW]}}, KC0[2].W
44 ; R600-DAG: MUL NON-IEEE T{{[0-9]\.[XYZW]}}, KC0[2].W, PS
45 ; R600-DAG: RECIPSQRT_CLAMPED * T{{[0-9]\.[XYZW]}}, KC0[3].X
46 ; R600-DAG: MUL NON-IEEE T{{[0-9]\.[XYZW]}}, KC0[3].X, PS
60 ; R600-DAG: RECIPSQRT_CLAMPED * T{{[0-9]\.[XYZW]}}, KC0[3].Y
61 ; R600-DAG: MUL NON-IEEE T{{[0-9]\.[XYZW]}}, KC0[3].Y, PS
62 ; R600-DAG: RECIPSQRT_CLAMPED * T{{[0-9]\.[XYZW]}}, KC0[3].Z
[all …]
Damdgpu.private-memory.ll11 ; RUN: llc -march=r600 -mcpu=cypress < %s | FileCheck %s -check-prefix=R600 -check-prefix=FUNC
21 ; R600: LDS_WRITE
22 ; R600: LDS_WRITE
23 ; R600: LDS_READ
24 ; R600: LDS_READ
160 ; R600-NOT: MOVA_INT
191 ; R600-NOT: MOVA_INT
228 ; R600: MOVA_INT
249 ; R600: MOVA_INT
273 ; R600-NOT: [[CHAN]]+
[all …]
Dfmul.ll3 ; RUN: llc -march=r600 -mcpu=redwood < %s | FileCheck -check-prefix=R600 -check-prefix=FUNC %s
8 ; R600: MUL_IEEE {{\** *}}{{T[0-9]+\.[XYZW]}}, KC0[2].Z, KC0[2].W
16 declare float @llvm.R600.load.input(i32) readnone
24 ; R600: MUL_IEEE {{\** *}}T{{[0-9]+\.[XYZW]}}
25 ; R600: MUL_IEEE {{\** *}}T{{[0-9]+\.[XYZW]}}
39 ; R600: MUL_IEEE {{\** *}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
40 ; R600: MUL_IEEE {{\** *}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
41 ; R600: MUL_IEEE {{\** *}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
42 ; R600: MUL_IEEE {{\** *}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
Dfneg-fabs.ll3 ; RUN: llc -march=r600 -mcpu=redwood < %s | FileCheck -check-prefix=R600 -check-prefix=FUNC %s
33 ; R600-NOT: AND
34 ; R600: |PV.{{[XYZW]}}|
35 ; R600: -PV
47 ; R600-NOT: AND
48 ; R600: |PV.{{[XYZW]}}|
49 ; R600: -PV
80 ; R600: |{{(PV|T[0-9])\.[XYZW]}}|
81 ; R600: -PV
82 ; R600: |{{(PV|T[0-9])\.[XYZW]}}|
[all …]
Dr600-encoding.ll2 ; RUN: llc < %s -march=r600 -show-mc-encoding -mcpu=rs880 | FileCheck --check-prefix=R600 %s
4 ; The earliest R600 GPUs have a slightly different encoding than the rest of
10 ; R600: {{^}}test:
11 ; R600: MUL_IEEE {{[ *TXYZWPVxyzw.,0-9]+}} ; encoding: [{{0x[0-9a-f]+,0x[0-9a-f]+,0x[0-9a-f]+,0x[0-…
19 call void @llvm.R600.store.swizzle(<4 x float> %vec, i32 0, i32 0)
23 declare void @llvm.R600.store.swizzle(<4 x float>, i32, i32)
Dfsub.ll3 ; RUN: llc -march=r600 -mcpu=redwood < %s | FileCheck -check-prefix=R600 -check-prefix=FUNC %s
17 ; R600: ADD {{\** *}}T{{[0-9]+\.[XYZW]}}, KC0[2].Z, -KC0[2].W
26 declare float @llvm.R600.load.input(i32) readnone
31 ; R600-DAG: ADD {{\** *}}T{{[0-9]+\.[XYZW]}}, KC0[3].X, -KC0[3].Z
32 ; R600-DAG: ADD {{\** *}}T{{[0-9]+\.[XYZW]}}, KC0[2].W, -KC0[3].Y
43 ; R600: ADD {{\** *}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], -T[0-9]+\.[XYZW]}}
44 ; R600: ADD {{\** *}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], -T[0-9]+\.[XYZW]}}
45 ; R600: ADD {{\** *}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], -T[0-9]+\.[XYZW]}}
46 ; R600: ADD {{\** *}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], -T[0-9]+\.[XYZW]}}
Dffloor.ll3 ; RUN: llc -march=r600 -mcpu=redwood < %s | FileCheck -check-prefix=R600 -check-prefix=FUNC %s
7 ; R600: FLOOR
30 ; R600: FLOOR
31 ; R600: FLOOR
32 ; R600: FLOOR
33 ; R600: FLOOR
Dcall_fs.ll3 ; RUN: llc < %s -march=r600 -mcpu=rv710 -show-mc-encoding -o - | FileCheck --check-prefix=R600 %s
8 ; R600: .long 257
9 ; R600: {{^}}call_fs:
10 ; R600:CALL_FS ; encoding: [0x00,0x00,0x00,0x00,0x00,0x00,0x80,0x89]
Datomic_load_sub.ll3 ; RUN: llc -march=r600 -mcpu=redwood < %s | FileCheck -check-prefix=R600 -check-prefix=FUNC %s
6 ; R600: LDS_SUB *
14 ; R600: LDS_SUB *
23 ; R600: LDS_SUB_RET *
32 ; R600: LDS_SUB_RET *
Datomic_load_add.ll3 ; RUN: llc -march=r600 -mcpu=redwood < %s | FileCheck -check-prefix=R600 -check-prefix=FUNC %s
6 ; R600: LDS_ADD *
14 ; R600: LDS_ADD *
23 ; R600: LDS_ADD_RET *
32 ; R600: LDS_ADD_RET *
Dloop-idiom.ll1 ; RUN: opt -basicaa -loop-idiom -S < %s -march=r600 -mcpu=redwood | FileCheck --check-prefix=R600 -…
7 ; implementations of these for R600.
10 ; R600-NOT: {{^}}llvm.memcpy
32 ; R600-NOT: {{^}}llvm.memset
33 ; R600-NOT: {{^}}memset_pattern16:
/external/llvm/lib/Target/AMDGPU/
DR600Intrinsics.td1 //===-- R600Intrinsics.td - R600 Instrinsic defs -------*- tablegen -*-----===//
10 // R600 Intrinsic Definitions
15 let TargetPrefix = "R600", isTarget = 1 in {
20 } // End TargetPrefix = "R600", isTarget = 1

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