/external/llvm/lib/Target/X86/MCTargetDesc/ |
D | X86MCTargetDesc.cpp | 109 X86::RCX, X86::RDX, X86::RSI, X86::RDI, X86::RBP, X86::RSP, in initLLVMToSEHAndCVRegMapping() 295 case X86::DH: case X86::DL: case X86::DX: case X86::EDX: case X86::RDX: in getX86SubSuperRegisterOrZero() 307 case X86::DH: case X86::DL: case X86::DX: case X86::EDX: case X86::RDX: in getX86SubSuperRegisterOrZero() 344 case X86::DH: case X86::DL: case X86::DX: case X86::EDX: case X86::RDX: in getX86SubSuperRegisterOrZero() 380 case X86::DH: case X86::DL: case X86::DX: case X86::EDX: case X86::RDX: in getX86SubSuperRegisterOrZero() 416 case X86::DH: case X86::DL: case X86::DX: case X86::EDX: case X86::RDX: in getX86SubSuperRegisterOrZero() 417 return X86::RDX; in getX86SubSuperRegisterOrZero()
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/external/swiftshader/third_party/LLVM/lib/Target/X86/ |
D | X86InstrArithmetic.td | 65 let Defs = [RAX,RDX,EFLAGS], Uses = [RAX], neverHasSideEffects = 1 in 67 "mul{q}\t$src", // RAX,RDX = RAX*GR64 68 [/*(set RAX, RDX, EFLAGS, (X86umul_flag RAX, GR64:$src))*/]>; 89 let Defs = [RAX,RDX,EFLAGS], Uses = [RAX], neverHasSideEffects = 1 in 91 "mul{q}\t$src", []>; // RAX,RDX = RAX*[mem64] 104 let Defs = [RAX,RDX,EFLAGS], Uses = [RAX], neverHasSideEffects = 1 in 106 // RAX,RDX = RAX*GR64 118 let Defs = [RAX,RDX,EFLAGS], Uses = [RAX], neverHasSideEffects = 1 in 120 "imul{q}\t$src", []>; // RAX,RDX = RAX*[mem64] 253 // RDX:RAX/r64 = RAX,RDX [all …]
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D | X86RegisterInfo.cpp | 365 X86::RAX, X86::RDX, X86::RBX, X86::R12, in getCalleeSavedRegs() 671 case X86::DH: case X86::DL: case X86::DX: case X86::EDX: case X86::RDX: in getX86SubSuperRegister() 683 case X86::DH: case X86::DL: case X86::DX: case X86::EDX: case X86::RDX: in getX86SubSuperRegister() 720 case X86::DH: case X86::DL: case X86::DX: case X86::EDX: case X86::RDX: in getX86SubSuperRegister() 756 case X86::DH: case X86::DL: case X86::DX: case X86::EDX: case X86::RDX: in getX86SubSuperRegister() 792 case X86::DH: case X86::DL: case X86::DX: case X86::EDX: case X86::RDX: in getX86SubSuperRegister() 793 return X86::RDX; in getX86SubSuperRegister()
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D | X86InstrSystem.td | 16 let Defs = [RAX, RDX] in 19 let Defs = [RAX, RCX, RDX] in 405 let Defs = [RDX, RAX], Uses = [RCX] in 408 let Uses = [RDX, RAX, RCX] in 411 let Uses = [RDX, RAX] in { 428 let Defs = [RAX, RDI], Uses = [RDX, RDI] in 433 let Defs = [RSI, RDI], Uses = [RBX, RDX, RSI, RDI] in { 445 let Defs = [RAX, RDX, RSI], Uses = [RAX, RSI] in
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D | X86RegisterInfo.td | 125 def RDX : RegisterWithSubRegs<"rdx", [EDX]>, DwarfRegNum<[1, -2, -2]>; 313 (add RAX, RCX, RDX, RSI, RDI, R8, R9, R10, R11, 347 def GR64_ABCD : RegisterClass<"X86", [i64], 64, (add RAX, RCX, RDX, RBX)> { 356 def GR64_TC : RegisterClass<"X86", [i64], 64, (add RAX, RCX, RDX, RSI, RDI, 363 def GR64_TCW64 : RegisterClass<"X86", [i64], 64, (add RAX, RCX, RDX, 387 (add RAX, RCX, RDX, RSI, RDI, RBX, RBP, RSP, RIP)> {
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D | X86CallingConv.td | 35 CCIfType<[i64], CCAssignToReg<[RAX, RDX]>>, 148 CCIfType<[i64], CCAssignToReg<[RDI, RSI, RDX, RCX, R8 , R9 ]>>, 206 CCIfSRet<CCIfType<[i64], CCAssignToRegWithShadow<[RDX , R8 , R9 ], 209 CCIfType<[i64], CCAssignToRegWithShadow<[RCX , RDX , R8 , R9 ], 215 [RCX , RDX , R8 , R9 ]>>,
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D | X86GenRegisterInfo.inc | 129 RDX = 110, 277 const unsigned DH_Overlaps[] = { X86::DH, X86::DX, X86::EDX, X86::RDX, 0 }; 280 const unsigned DL_Overlaps[] = { X86::DL, X86::DX, X86::EDX, X86::RDX, 0 }; 290 const unsigned DX_Overlaps[] = { X86::DX, X86::DH, X86::DL, X86::EDX, X86::RDX, 0 }; 296 const unsigned EDX_Overlaps[] = { X86::EDX, X86::DH, X86::DL, X86::DX, X86::RDX, 0 }; 358 const unsigned RDX_Overlaps[] = { X86::RDX, X86::DH, X86::DL, X86::DX, X86::EDX, 0 }; 503 const unsigned DH_SuperRegsSet[] = { X86::DX, X86::EDX, X86::RDX, 0 }; 506 const unsigned DL_SuperRegsSet[] = { X86::DX, X86::EDX, X86::RDX, 0 }; 507 const unsigned DX_SuperRegsSet[] = { X86::EDX, X86::RDX, 0 }; 513 const unsigned EDX_SuperRegsSet[] = { X86::RDX, 0 }; [all …]
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D | X86InstrControl.td | 215 let Defs = [RAX, RCX, RDX, RSI, RDI, R8, R9, R10, R11, 247 let Defs = [RAX, RCX, RDX, R8, R9, R10, R11, 280 let Defs = [RAX, RCX, RDX, R8, R9, R10, R11,
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/external/libunwind/src/x86_64/ |
D | init.h | 50 c->dwarf.loc[RDX] = REG_INIT_LOC(c, rdx, RDX); in common_init()
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D | unwind_i.h | 40 #define RDX 1 macro
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D | Gregs.c | 104 loc = c->dwarf.loc[(reg == UNW_X86_64_RAX) ? RAX : RDX]; in tdep_access_reg()
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/external/llvm/lib/Target/X86/ |
D | X86CallingConv.td | 41 CCIfType<[i64], CCAssignToReg<[RAX, RDX, RCX]>>, 186 CCIfType<[i64], CCAssignToReg<[R15, RBP, RAX, RDX]>> 204 CCIfType<[i64], CCAssignToReg<[RAX, RDX, RCX, R8]>>, 233 CCIfType<[i64], CCAssignToReg<[RBX, RBP, RDI, RSI, RDX, RCX, R8, R9, 312 CCIfType<[i64], CCAssignToReg<[RDI, RSI, RDX, RCX, R8 , R9 ]>>, 374 RDI, RSI, RDX, RCX, R8, R9, 418 CCIfSRet<CCIfType<[i64], CCAssignToRegWithShadow<[RDX , R8 , R9 ], 421 CCIfType<[i64], CCAssignToRegWithShadow<[RCX , RDX , R8 , R9 ], 427 [RCX , RDX , R8 , R9 ]>>, 476 CCIfType<[i64], CCAssignToReg<[R15, RBP, RSI, RDX, RCX, R8]>>, [all …]
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D | X86InstrArithmetic.td | 78 // RAX,RDX = RAX*GR64 79 let Defs = [RAX,RDX,EFLAGS], Uses = [RAX], hasSideEffects = 0 in 82 [/*(set RAX, RDX, EFLAGS, (X86umul_flag RAX, GR64:$src))*/], 104 // RAX,RDX = RAX*[mem64] 105 let Defs = [RAX,RDX,EFLAGS], Uses = [RAX] in 123 // RAX,RDX = RAX*GR64 124 let Defs = [RAX,RDX,EFLAGS], Uses = [RAX] in 143 // RAX,RDX = RAX*[mem64] 144 let Defs = [RAX,RDX,EFLAGS], Uses = [RAX] in 306 // RDX:RAX/r64 = RAX,RDX [all …]
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D | X86RegisterInfo.td | 130 def RDX : X86Reg<"rdx", 2, [EDX]>, DwarfRegNum<[1, -2, -2]>; 349 (add RAX, RCX, RDX, RSI, RDI, R8, R9, R10, R11, 373 def GR64_ABCD : RegisterClass<"X86", [i64], 64, (add RAX, RCX, RDX, RBX)>; 375 def GR64_TC : RegisterClass<"X86", [i64], 64, (add RAX, RCX, RDX, RSI, RDI, 377 def GR64_TCW64 : RegisterClass<"X86", [i64], 64, (add RAX, RCX, RDX, 396 (add RAX, RCX, RDX, RSI, RDI, RBX, RBP, RSP, RIP)>;
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D | X86InstrSystem.td | 17 let Defs = [RAX, RDX] in 21 let Defs = [RAX, RCX, RDX] in 444 let Defs = [RAX, RDX], Uses = [ECX] in 537 let Defs = [RAX, RDI], Uses = [RDX, RDI] in 542 let Defs = [RSI, RDI], Uses = [RBX, RDX, RSI, RDI] in { 554 let Defs = [RAX, RDX, RSI], Uses = [RAX, RSI] in 617 let Uses = [RAX, RBX, RCX, RDX], Defs = [RAX, RBX, RCX] in {
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/external/strace/linux/x86_64/ |
D | userent.h | 13 XLAT(8*RDX),
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/external/kernel-headers/original/uapi/asm-x86/asm/ |
D | ptrace-abi.h | 46 #define RDX 96 macro
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/external/valgrind/coregrind/m_sigframe/ |
D | sigframe-amd64-darwin.c | 105 SC2(__rdx,RDX); in synthesize_ucontext() 133 SC2(RDX,__rdx); in restore_from_ucontext()
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/external/swiftshader/third_party/LLVM/lib/Target/X86/Disassembler/ |
D | X86DisassemblerDecoder.h | 163 ENTRY(RDX) \ 181 ENTRY(RDX) \
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/external/lzma/Asm/x86/ |
D | 7zAsm.asm | 68 r2 equ RDX
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/external/llvm/test/CodeGen/X86/ |
D | 2010-02-23-RematImplicitSubreg.ll | 6 ; %DL<def> = MOV8rr %reg1038<kill>, %RDX<imp-def>
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/external/swiftshader/third_party/LLVM/test/CodeGen/X86/ |
D | 2010-02-23-RematImplicitSubreg.ll | 6 ; %DL<def> = MOV8rr %reg1038<kill>, %RDX<imp-def>
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/external/llvm/lib/Target/X86/Disassembler/ |
D | X86DisassemblerDecoder.h | 173 ENTRY(RDX) \ 191 ENTRY(RDX) \
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/external/capstone/arch/X86/ |
D | X86DisassemblerDecoder.h | 186 ENTRY(RDX) \ 204 ENTRY(RDX) \
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/external/google-breakpad/src/common/android/ |
D | breakpad_getcontext_unittest.cc | 133 CHECK_REG(RDX); in TEST()
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