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Searched refs:RDval (Results 1 – 19 of 19) sorted by relevance

/external/valgrind/none/tests/mips64/
Dbranches.c130 #define TESTINST4(instruction, RDval, RSval, RTval, RD, RS, RT) \ argument
138 instruction" $"#RS", $"#RT", end"instruction#RDval "\n\t" \
141 "end"instruction#RDval":" "\n\t" \
146 : "r" (RSval), "r" (RTval), "r" (RDval) \
150 out, RDval, RSval, RTval); \
153 #define TESTINST5(instruction, RDval, RSval, RD, RS) \ argument
160 instruction" $"#RS", end"instruction#RDval "\n\t" \
163 "end"instruction#RDval":" "\n\t" \
168 : "r" (RSval), "r" (RDval) \
172 out, RDval, RSval); \
[all …]
Dmacro_fpu.h217 #define TESTINST1s(instruction, RDval) \ argument
226 instruction" end"instruction"s"#RDval "\n\t" \
229 "end"instruction"s"#RDval":" "\n\t" \
241 #define TESTINST1d(instruction, RDval) \ argument
250 instruction" end"instruction"d"#RDval "\n\t" \
253 "end"instruction"d"#RDval":" "\n\t" \
265 #define TESTINST2s(instruction, RDval) \ argument
274 instruction" end"instruction"s"#RDval "\n\t" \
276 "end"instruction"s"#RDval":" "\n\t" \
288 #define TESTINST2d(instruction, RDval) \ argument
[all …]
Dbranch_and_jump_instructions.c107 #define TEST3(instruction, RDval, RSval, RTval, RD, RS, RT) \ argument
115 instruction" $"#RS", $"#RT", end"instruction#RDval "\n\t" \
118 "end"instruction#RDval":" "\n\t" \
123 : "r" (RSval), "r" (RTval), "r" (RDval) \
130 #define TEST4(instruction, RDval, RSval, RD, RS) \ argument
137 instruction" $"#RS", end"instruction#RDval "\n\t" \
140 "end"instruction#RDval":" "\n\t" \
145 : "r" (RSval), "r" (RDval) \
152 #define TEST5(instruction, RDval, RSval, RD, RS) \ argument
159 instruction" $"#RS", end21"instruction#RDval "\n\t" \
[all …]
Dmove_instructions.stdout.exp-LE1163 --- MOVF --- if FPConditionalCode(cc) == 0 then out = RSval else out = RDval
1164 movf :: RDval: 0xaaaaaaaa, RSval: 0x80000000, out: 0xffffffffaaaaaaaa
1165 movf :: RDval: 0xccccffff, RSval: 0xffffffff, out: 0xffffffffccccffff
1166 movf :: RDval: 0xffffaaaa, RSval: 0xaaaaffff, out: 0xffffffffffffaaaa
1167 movf :: RDval: 0x0, RSval: 0xffffffff, out: 0x0
1168 movf :: RDval: 0xaaaaaaaa, RSval: 0x80000000, out: 0xffffffff80000000
1169 movf :: RDval: 0xccccffff, RSval: 0xffffffff, out: 0xffffffffffffffff
1170 movf :: RDval: 0xffffaaaa, RSval: 0xaaaaffff, out: 0xffffffffaaaaffff
1171 movf :: RDval: 0x0, RSval: 0xffffffff, out: 0xffffffffffffffff
1172 movf :: RDval: 0xaaaaaaaa, RSval: 0x80000000, out: 0xffffffff80000000
[all …]
Dmove_instructions.stdout.exp-BE1163 --- MOVF --- if FPConditionalCode(cc) == 0 then out = RSval else out = RDval
1164 movf :: RDval: 0xaaaaaaaa, RSval: 0x80000000, out: 0xffffffffaaaaaaaa
1165 movf :: RDval: 0xccccffff, RSval: 0xffffffff, out: 0xffffffffccccffff
1166 movf :: RDval: 0xffffaaaa, RSval: 0xaaaaffff, out: 0xffffffffffffaaaa
1167 movf :: RDval: 0x0, RSval: 0xffffffff, out: 0x0
1168 movf :: RDval: 0xaaaaaaaa, RSval: 0x80000000, out: 0xffffffff80000000
1169 movf :: RDval: 0xccccffff, RSval: 0xffffffff, out: 0xffffffffffffffff
1170 movf :: RDval: 0xffffaaaa, RSval: 0xaaaaffff, out: 0xffffffffaaaaffff
1171 movf :: RDval: 0x0, RSval: 0xffffffff, out: 0xffffffffffffffff
1172 movf :: RDval: 0xaaaaaaaa, RSval: 0x80000000, out: 0xffffffff80000000
[all …]
Dbranches.stdout.exp76 --- BEQ --- if RSval == RTval then out = RDval + 1 else out = RDval + 6
93 --- BNE --- if RSval != RTval then out = RDval + 1 else out = RDval + 6
110 --- BEQZ --- if RSval == 0 then out = RDval + 1 else out = RDval + 6
127 --- BGEZ --- if RSval >= 0 then out = RDval + 1 else out = RDval + 6
144 --- BGTZ --- if RSval > 0 then out = RDval + 1 else out = RDval + 6
161 --- BLEZ --- if RSval <= 0 then out = RDval + 1 else out = RDval + 6
178 --- BLTZ --- if RSval < 0 then out = RDval + 1 else out = RDval + 6
195 --- BGEZAL --- if RSval >= 0 then out = RDval + 6 else out = RDval + 5
212 --- BLTZAL --- if RSval < 0 then out = RDval + 6 else out = RDval + 5
229 --- BNEZ --- if RSval != 0 then out = RDval + 1 else out = RDval + 6
[all …]
Dmove_instructions.c178 #define TEST5(instruction, RDval, RSval, RD, RS) \ argument
188 : "r" (RDval), "r" (RSval), "f" (fs1_f[i]), "f" (fs2_f[i]) \
192 instruction, RDval, RSval, out); \
Dbranch_and_jump_instructions.stdout.exp515 --- BEQ --- if RSval == RTval then out = RDval + 1 else out = RDval + 6
532 --- BGEZ --- if RSval >= 0 then out = RDval + 1 else out = RDval + 9
549 --- BGEZAL --- if RSval >= 0 then out = RDval + 1 else out = RDval + 6
566 --- BGTZ --- if RSval > 0 then out = RDval + 1 else out = RDval + 9
583 --- BLEZ --- if RSval <= 0 then out = RDval + 1 else out = RDval + 9
600 --- BLTZ --- if RSval < 0 then out = RDval + 1 else out = RDval + 9
617 --- BLTZAL --- if RSval < 0 then out = RDval + 1 else out = RDval + 6
634 --- BNE --- if RSval != RTval then out = RDval + 1 else out = RDval + 6
/external/valgrind/none/tests/mips32/
Dfpu_branches.c44 #define TESTINST1s(instruction, RDval) \ argument
52 instruction" end"instruction"s"#RDval "\n\t" \
55 "end"instruction"s"#RDval":" "\n\t" \
66 #define TESTINST1d(instruction, RDval) \ argument
74 instruction" end"instruction"d"#RDval "\n\t" \
77 "end"instruction"d"#RDval":" "\n\t" \
88 #define TESTINST2s(instruction, RDval) \ argument
96 instruction" end"instruction"s"#RDval "\n\t" \
98 "end"instruction"s"#RDval":" "\n\t" \
109 #define TESTINST2d(instruction, RDval) \ argument
[all …]
Dbranches.c129 #define TESTINST4(instruction, RDval, RSval, RTval, RD, RS, RT) \ argument
138 instruction" $" #RS ", $" #RT ", end"instruction#RDval"\n\t" \
141 "end"instruction#RDval":\n\t" \
146 : "r" (RSval), "r" (RTval), "r" (RDval) \
153 #define TESTINST5(instruction, RDval, RSval, RD, RS) \ argument
161 instruction" $" #RS ", end"instruction#RDval"\n\t" \
164 "end"instruction#RDval":\n\t" \
169 : "r" (RSval), "r" (RDval) \
176 #define TESTINST6(instruction, RDval, RSval, RD, RS) \ argument
184 instruction" $" #RS ", end21"instruction#RDval"\n\t" \
[all …]
DMoveIns.stdout.exp-BE114 movf $t0, $t1, $fcc0 :: out: 0x0, RDval: 0x0, RSval: 0xffffffff, cc: 1
115 movf $t0, $t1, $fcc0 :: out: 0xffffffff, RDval: 0xffffffff, RSval: 0xffffffff, cc: 0
116 movf $t0, $t1, $fcc0 :: out: 0x22b, RDval: 0x22b, RSval: 0xffffffff, cc: 1
117 movf $t0, $t1, $fcc0 :: out: 0x5, RDval: 0x0, RSval: 0x5, cc: 0
118 movf $t0, $t1, $fcc0 :: out: 0x0, RDval: 0x0, RSval: 0xffffffff, cc: 1
119 movf $t0, $t1, $fcc0 :: out: 0x19, RDval: 0xffffffff, RSval: 0x19, cc: 0
120 movf $t0, $t1, $fcc0 :: out: 0xffffffff, RDval: 0xffffffff, RSval: 0x0, cc: 1
121 movf $t0, $t1, $fcc0 :: out: 0x42, RDval: 0xffffffff, RSval: 0x42, cc: 0
122 movf $t0, $t1, $fcc4 :: out: 0xffffffff, RDval: 0x0, RSval: 0xffffffff, cc: 1
123 movf $t0, $t1, $fcc4 :: out: 0xffffffff, RDval: 0xffffffff, RSval: 0xffffffff, cc: 0
[all …]
DMoveIns.stdout.exp-mips32r2-BE148 movf $t0, $t1, $fcc0 :: out: 0x0, RDval: 0x0, RSval: 0xffffffff, cc: 1
149 movf $t0, $t1, $fcc0 :: out: 0xffffffff, RDval: 0xffffffff, RSval: 0xffffffff, cc: 0
150 movf $t0, $t1, $fcc0 :: out: 0x22b, RDval: 0x22b, RSval: 0xffffffff, cc: 1
151 movf $t0, $t1, $fcc0 :: out: 0x5, RDval: 0x0, RSval: 0x5, cc: 0
152 movf $t0, $t1, $fcc0 :: out: 0x0, RDval: 0x0, RSval: 0xffffffff, cc: 1
153 movf $t0, $t1, $fcc0 :: out: 0x19, RDval: 0xffffffff, RSval: 0x19, cc: 0
154 movf $t0, $t1, $fcc0 :: out: 0xffffffff, RDval: 0xffffffff, RSval: 0x0, cc: 1
155 movf $t0, $t1, $fcc0 :: out: 0x42, RDval: 0xffffffff, RSval: 0x42, cc: 0
156 movf $t0, $t1, $fcc4 :: out: 0xffffffff, RDval: 0x0, RSval: 0xffffffff, cc: 1
157 movf $t0, $t1, $fcc4 :: out: 0xffffffff, RDval: 0xffffffff, RSval: 0xffffffff, cc: 0
[all …]
DMoveIns.stdout.exp-mips32r2-LE148 movf $t0, $t1, $fcc0 :: out: 0x0, RDval: 0x0, RSval: 0xffffffff, cc: 1
149 movf $t0, $t1, $fcc0 :: out: 0xffffffff, RDval: 0xffffffff, RSval: 0xffffffff, cc: 0
150 movf $t0, $t1, $fcc0 :: out: 0x22b, RDval: 0x22b, RSval: 0xffffffff, cc: 1
151 movf $t0, $t1, $fcc0 :: out: 0x5, RDval: 0x0, RSval: 0x5, cc: 0
152 movf $t0, $t1, $fcc0 :: out: 0x0, RDval: 0x0, RSval: 0xffffffff, cc: 1
153 movf $t0, $t1, $fcc0 :: out: 0x19, RDval: 0xffffffff, RSval: 0x19, cc: 0
154 movf $t0, $t1, $fcc0 :: out: 0xffffffff, RDval: 0xffffffff, RSval: 0x0, cc: 1
155 movf $t0, $t1, $fcc0 :: out: 0x42, RDval: 0xffffffff, RSval: 0x42, cc: 0
156 movf $t0, $t1, $fcc4 :: out: 0xffffffff, RDval: 0x0, RSval: 0xffffffff, cc: 1
157 movf $t0, $t1, $fcc4 :: out: 0xffffffff, RDval: 0xffffffff, RSval: 0xffffffff, cc: 0
[all …]
DMoveIns.c159 #define TESTINSNMOVE2(instruction, RDval, RSval, RD, RS, cc) \ argument
173 : "r" (RSval), "r" (RDval), "r" (cc) \
177 instruction, out, RDval, RSval, cc); \
Dmips32_dspr2.c113 #define TESTDSPINST_BPOSGE32(instruction, RDval, POSval, RD, POSreg) \ argument
121 instruction" end"instruction#RDval" \n\t" \
124 "end"instruction#RDval": \n\t" \
128 : "r" (POSval), "r" (RDval) \
Dmips32_dsp.c97 #define TESTDSPINST_BPOSGE32(instruction, RDval, POSval, RD, POSreg) \ argument
105 instruction" end"instruction#RDval" \n\t" \
108 "end"instruction#RDval": \n\t" \
112 : "r" (POSval), "r" (RDval) \
/external/valgrind/none/tests/arm/
Dv6intARM.c100 #define TESTINST4_2OUT(instruction, RDval, RD2val, RMval, RSval, RD, RD2, RM, RS, carryin) \ argument
119 : "r" (RDval), "r" (RD2val), "r" (RMval), "r" (RSval), "r" (carryin) \
Dv6intThumb.c47 #define TESTINST1x(instruction, RDval, RD, cvin) \ argument
59 : "r" (gen_cvin(cvin)), "r"(RDval) \
106 #define TESTINST2x(instruction, RDval, RMval, RD, RM, cvin) \ argument
119 : "r" (RMval), "r" (gen_cvin(cvin)), "r"(RDval) \
190 #define TESTINST4_2OUT(instruction, RDval, RD2val, RMval, RSval, RD, RD2, RM, RS, cvin) \ argument
207 : "r" (RDval), "r" (RD2val), "r" (RMval), "r" (RSval), "r" (gen_cvin(cvin)) \
Dv6media.c109 #define TESTINST4_2OUT(instruction, RDval, RD2val, RMval, RSval, RD, RD2, RM, RS, carryin) \ argument
126 : "r" (RDval), "r" (RD2val), "r" (RMval), "r" (RSval), "r" (gen_cin(carryin)) \