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Searched refs:RESULT (Results 1 – 25 of 122) sorted by relevance

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/external/swiftshader/third_party/subzero/tests_lit/llvm2ice_tests/
Dicmp-with-zero.ll107 ; CHECK: mov [[RESULT:.*]],0x0
108 ; CHECK-NEXT: cmp [[RESULT]],0x0
110 ; OPTM1: mov [[RESULT:.*]],0x0
111 ; OPTM1-NEXT: cmp [[RESULT]],0x0
128 ; CHECK: mov [[RESULT:.*]],0x1
129 ; CHECK-NEXT: cmp [[RESULT]],0x0
131 ; OPTM1: mov [[RESULT:.*]],0x1
132 ; OPTM1-NEXT: cmp [[RESULT]],0x0
150 ; CHECK: mov [[RESULT:.*]],0x0
151 ; CHECK-NEXT: cmp [[RESULT]],0x0
[all …]
/external/llvm/test/CodeGen/AMDGPU/
Dllvm.amdgcn.rcp.ll18 ; SI: v_rcp_f32_e32 [[RESULT:v[0-9]+]], s{{[0-9]+}}
19 ; SI-NOT: [[RESULT]]
20 ; SI: buffer_store_dword [[RESULT]]
28 ; SI: v_rcp_f32_e32 [[RESULT:v[0-9]+]], s{{[0-9]+}}
29 ; SI-NOT: [[RESULT]]
30 ; SI: buffer_store_dword [[RESULT]]
65 ; SI: v_rcp_f64_e32 [[RESULT:v\[[0-9]+:[0-9]+\]]], s{{\[[0-9]+:[0-9]+\]}}
66 ; SI-NOT: [[RESULT]]
67 ; SI: buffer_store_dwordx2 [[RESULT]]
75 ; SI: v_rcp_f64_e32 [[RESULT:v\[[0-9]+:[0-9]+\]]], s{{\[[0-9]+:[0-9]+\]}}
[all …]
Dcttz_zero_undef.ll15 ; EG: MEM_RAT_CACHELESS STORE_RAW [[RESULT:T[0-9]+\.[XYZW]]]
16 ; EG: FFBL_INT {{\*? *}}[[RESULT]]
25 ; SI: v_ffbl_b32_e32 [[RESULT:v[0-9]+]], [[VAL]]
26 ; SI: buffer_store_dword [[RESULT]],
28 ; EG: MEM_RAT_CACHELESS STORE_RAW [[RESULT:T[0-9]+\.[XYZW]]]
29 ; EG: FFBL_INT {{\*? *}}[[RESULT]]
43 ; EG: MEM_RAT_CACHELESS STORE_RAW [[RESULT:T[0-9]+]]{{\.[XYZW]}}
44 ; EG: FFBL_INT {{\*? *}}[[RESULT]]
45 ; EG: FFBL_INT {{\*? *}}[[RESULT]]
61 ; EG: MEM_RAT_CACHELESS STORE_RAW [[RESULT:T[0-9]+]]{{\.[XYZW]}}
[all …]
Dsetcc-opt.ll8 ; GCN-NEXT: v_cndmask_b32_e64 [[RESULT:v[0-9]+]], 0, 1, vcc
9 ; GCN-NEXT:buffer_store_byte [[RESULT]]
25 ; GCN-NEXT: v_cndmask_b32_e64 [[RESULT:v[0-9]+]], 0, 1, vcc
26 ; GCN-NEXT: buffer_store_byte [[RESULT]]
42 ; GCN-NEXT: v_cndmask_b32_e64 [[RESULT:v[0-9]+]], 0, 1, vcc
43 ; GCN-NEXT: buffer_store_byte [[RESULT]]
56 ; GCN-NEXT: v_cndmask_b32_e64 [[RESULT:v[0-9]+]], 0, 1, vcc
57 ; GCN-NEXT: buffer_store_byte [[RESULT]]
70 ; GCN-NEXT: v_cndmask_b32_e64 [[RESULT:v[0-9]+]], 0, 1, vcc
71 ; GCN-NEXT: buffer_store_byte [[RESULT]]
[all …]
Dtrunc-cmp-constant.ll24 ; SI-NEXT: v_cndmask_b32_e64 [[RESULT:v[0-9]+]], 0, 1, [[NEG]]
25 ; SI: buffer_store_byte [[RESULT]]
35 ; SI: v_mov_b32_e32 [[RESULT:v[0-9]+]], 0{{$}}
36 ; SI: buffer_store_byte [[RESULT]]
47 ; SI: v_and_b32_e32 [[RESULT:v[0-9]+]], 1, [[LOAD]]
48 ; SI: buffer_store_byte [[RESULT]]
59 ; SI: v_and_b32_e32 [[RESULT:v[0-9]+]], 1, [[LOAD]]
60 ; SI: buffer_store_byte [[RESULT]]
70 ; SI: v_mov_b32_e32 [[RESULT:v[0-9]+]], 0{{$}}
71 ; SI: buffer_store_byte [[RESULT]]
[all …]
Dctpop.ll28 ; GCN: v_bcnt_u32_b32_e64 [[RESULT:v[0-9]+]], [[VAL]], 0
29 ; GCN: buffer_store_dword [[RESULT]],
44 ; SI: v_bcnt_u32_b32_e32 [[RESULT:v[0-9]+]], [[VAL0]], [[MIDRESULT]]
45 ; VI: v_bcnt_u32_b32_e64 [[RESULT:v[0-9]+]], [[VAL0]], [[MIDRESULT]]
46 ; GCN: buffer_store_dword [[RESULT]],
64 ; GCN-NEXT: v_bcnt_u32_b32_e64 [[RESULT:v[0-9]+]], [[VAL0]], s{{[0-9]+}}
65 ; GCN: buffer_store_dword [[RESULT]],
177 ; GCN: v_bcnt_u32_b32_e64 [[RESULT:v[0-9]+]], [[VAL]], 4
178 ; GCN: buffer_store_dword [[RESULT]],
192 ; GCN: v_bcnt_u32_b32_e64 [[RESULT:v[0-9]+]], [[VAL]], 4
[all …]
Dllvm.amdgcn.class.ll14 ; SI-NEXT: v_cndmask_b32_e64 [[RESULT:v[0-9]+]], 0, -1, vcc
15 ; SI-NEXT: buffer_store_dword [[RESULT]]
29 ; SI-NEXT: v_cndmask_b32_e64 [[RESULT:v[0-9]+]], 0, -1, [[CMP]]
30 ; SI-NEXT: buffer_store_dword [[RESULT]]
45 ; SI-NEXT: v_cndmask_b32_e64 [[RESULT:v[0-9]+]], 0, -1, [[CMP]]
46 ; SI-NEXT: buffer_store_dword [[RESULT]]
61 ; SI-NEXT: v_cndmask_b32_e64 [[RESULT:v[0-9]+]], 0, -1, [[CMP]]
62 ; SI-NEXT: buffer_store_dword [[RESULT]]
76 ; SI-NEXT: v_cndmask_b32_e64 [[RESULT:v[0-9]+]], 0, -1, [[COND]]
77 ; SI-NEXT: buffer_store_dword [[RESULT]]
[all …]
Dllvm.AMDGPU.clamp.ll10 ; SI: v_add_f32_e64 [[RESULT:v[0-9]+]], 0, [[ARG]] clamp{{$}}
11 ; SI: buffer_store_dword [[RESULT]]
23 ; SI: v_add_f32_e64 [[RESULT:v[0-9]+]], 0, |[[ARG]]| clamp{{$}}
24 ; SI: buffer_store_dword [[RESULT]]
35 ; SI: v_add_f32_e64 [[RESULT:v[0-9]+]], 0, -[[ARG]] clamp{{$}}
36 ; SI: buffer_store_dword [[RESULT]]
47 ; SI: v_add_f32_e64 [[RESULT:v[0-9]+]], 0, -|[[ARG]]| clamp{{$}}
48 ; SI: buffer_store_dword [[RESULT]]
Duse-sgpr-multiple-times.ll12 ; GCN: v_add_f32_e64 [[RESULT:v[0-9]+]], [[SGPR]], [[SGPR]]
13 ; GCN: buffer_store_dword [[RESULT]]
22 ; GCN: v_fma_f32 [[RESULT:v[0-9]+]], [[SGPR]], [[SGPR]], [[SGPR]]
23 ; GCN: buffer_store_dword [[RESULT]]
36 ; GCN: v_fma_f32 [[RESULT:v[0-9]+]], [[SGPR0]], [[SGPR0]], [[VGPR1]]
37 ; GCN: buffer_store_dword [[RESULT]]
76 ; GCN: v_fma_f32 [[RESULT:v[0-9]+]], [[VGPR1]], [[SGPR0]], [[SGPR0]]
77 ; GCN: buffer_store_dword [[RESULT]]
90 ; GCN: v_fma_f32 [[RESULT:v[0-9]+]], [[SGPR0]], [[VGPR1]], [[SGPR0]]
91 ; GCN: buffer_store_dword [[RESULT]]
[all …]
Dfract.ll12 ; GCN-SAFE: v_subrev_f32_e32 [[RESULT:v[0-9]+]], [[FLR]], [[INPUT]]
14 ; GCN-UNSAFE: v_fract_f32_e32 [[RESULT:v[0-9]+]], [[INPUT:v[0-9]+]]
16 ; GCN: buffer_store_dword [[RESULT]]
27 ; GCN-SAFE: v_sub_f32_e64 [[RESULT:v[0-9]+]], -[[INPUT]], [[FLR]]
29 ; GCN-UNSAFE: v_fract_f32_e64 [[RESULT:v[0-9]+]], -[[INPUT:v[0-9]+]]
31 ; GCN: buffer_store_dword [[RESULT]]
43 ; GCN-SAFE: v_sub_f32_e64 [[RESULT:v[0-9]+]], -|[[INPUT]]|, [[FLR]]
45 ; GCN-UNSAFE: v_fract_f32_e64 [[RESULT:v[0-9]+]], -|[[INPUT:v[0-9]+]]|
47 ; GCN: buffer_store_dword [[RESULT]]
Dshl_add_constant.ll9 ; SI: v_add_i32_e32 [[RESULT:v[0-9]+]], vcc, 36, [[REG]]
10 ; SI: buffer_store_dword [[RESULT]]
43 ; SI: v_add_i32_e32 [[RESULT:v[0-9]+]], vcc, 0xf9c, [[REG]]
44 ; SI: buffer_store_dword [[RESULT]]
60 ; SI: s_add_i32 [[RESULT:s[0-9]+]], [[SHL3]], [[Y]]
61 ; SI: s_addk_i32 [[RESULT]], 0x3d8
62 ; SI: v_mov_b32_e32 [[VRESULT:v[0-9]+]], [[RESULT]]
77 ; SI: s_add_i32 [[RESULT:s[0-9]+]], [[TMP]], 0x3d8
78 ; SI: v_mov_b32_e32 [[VRESULT:v[0-9]+]], [[RESULT]]
Dctlz_zero_undef.ll23 ; EG: MEM_RAT_CACHELESS STORE_RAW [[RESULT:T[0-9]+\.[XYZW]]]
24 ; EG: FFBH_UINT {{\*? *}}[[RESULT]]
33 ; SI: v_ffbh_u32_e32 [[RESULT:v[0-9]+]], [[VAL]]
34 ; SI: buffer_store_dword [[RESULT]],
36 ; EG: MEM_RAT_CACHELESS STORE_RAW [[RESULT:T[0-9]+\.[XYZW]]]
37 ; EG: FFBH_UINT {{\*? *}}[[RESULT]]
51 ; EG: MEM_RAT_CACHELESS STORE_RAW [[RESULT:T[0-9]+]]{{\.[XYZW]}}
52 ; EG: FFBH_UINT {{\*? *}}[[RESULT]]
53 ; EG: FFBH_UINT {{\*? *}}[[RESULT]]
69 ; EG: MEM_RAT_CACHELESS STORE_RAW [[RESULT:T[0-9]+]]{{\.[XYZW]}}
[all …]
Dfceil.ll14 ; EG: MEM_RAT_CACHELESS STORE_RAW [[RESULT:T[0-9]+\.[XYZW]]]
15 ; EG: CEIL {{\*? *}}[[RESULT]]
25 ; EG: MEM_RAT_CACHELESS STORE_RAW [[RESULT:T[0-9]+]]{{\.[XYZW]}}
26 ; EG: CEIL {{\*? *}}[[RESULT]]
27 ; EG: CEIL {{\*? *}}[[RESULT]]
55 ; EG: MEM_RAT_CACHELESS STORE_RAW [[RESULT:T[0-9]+]]{{\.[XYZW]}}
56 ; EG: CEIL {{\*? *}}[[RESULT]]
57 ; EG: CEIL {{\*? *}}[[RESULT]]
58 ; EG: CEIL {{\*? *}}[[RESULT]]
59 ; EG: CEIL {{\*? *}}[[RESULT]]
Dfp16_to_fp.ll9 ; SI: v_cvt_f32_f16_e32 [[RESULT:v[0-9]+]], [[VAL]]
10 ; SI: buffer_store_dword [[RESULT]]
22 ; SI: v_cvt_f64_f32_e32 [[RESULT:v\[[0-9]+:[0-9]+\]]], [[RESULT32]]
23 ; SI: buffer_store_dwordx2 [[RESULT]]
Dllvm.amdgcn.trig.preop.ll9 ; SI: v_trig_preop_f64 [[RESULT:v\[[0-9]+:[0-9]+\]]], [[SRC]], [[SEG]]
10 ; SI: buffer_store_dwordx2 [[RESULT]],
22 ; SI: v_trig_preop_f64 [[RESULT:v\[[0-9]+:[0-9]+\]]], [[SRC]], 7
23 ; SI: buffer_store_dwordx2 [[RESULT]],
Dmad-combine.ll24 ; SI-DENORM: v_fma_f32 [[RESULT:v[0-9]+]], [[A]], [[B]], [[C]]
30 ; SI-DENORM-SLOWFMAF: v_add_f32_e32 [[RESULT:v[0-9]+]], [[C]], [[TMP]]
32 ; SI-DENORM: buffer_store_dword [[RESULT]]
103 ; SI-DENORM: v_fma_f32 [[RESULT:v[0-9]+]], [[A]], [[B]], [[C]]
106 ; SI-DENORM-SLOWFMAF: v_add_f32_e32 [[RESULT:v[0-9]+]], [[TMP]], [[C]]
108 ; SI-DENORM: buffer_store_dword [[RESULT]]
133 ; SI-STD: v_mad_f32 [[RESULT:v[0-9]+]], [[A]], [[B]], -[[C]]
134 ; SI-DENORM: v_fma_f32 [[RESULT:v[0-9]+]], [[A]], [[B]], -[[C]]
137 ; SI-DENORM-SLOWFMAF: v_subrev_f32_e32 [[RESULT:v[0-9]+]], [[C]], [[TMP]]
139 ; SI: buffer_store_dword [[RESULT]]
[all …]
Dctpop64.ll30 ; SI-NEXT: v_bcnt_u32_b32_e32 [[RESULT:v[0-9]+]], v[[HIVAL]], [[MIDRESULT]]
31 ; VI-NEXT: v_bcnt_u32_b32_e64 [[RESULT:v[0-9]+]], v[[HIVAL]], [[MIDRESULT]]
32 ; GCN: buffer_store_dword [[RESULT]],
46 ; SI-NEXT: v_bcnt_u32_b32_e32 [[RESULT:v[0-9]+]], v[[HIVAL]], [[MIDRESULT]]
47 ; VI-NEXT: v_bcnt_u32_b32_e64 [[RESULT:v[0-9]+]], v[[HIVAL]], [[MIDRESULT]]
48 ; GCN-DAG: v_or_b32_e32 v[[RESULT_LO:[0-9]+]], s{{[0-9]+}}, [[RESULT]]
119 ; GCN-DAG: s_bcnt1_i32_b64 [[RESULT:s[0-9]+]], {{s\[}}[[LOVAL]]:[[HIVAL]]{{\]}}
121 ; GCN-DAG: v_mov_b32_e32 v[[VLO:[0-9]+]], [[RESULT]]
181 ; GCN: v_add_i32_e32 [[RESULT:v[0-9]+]], vcc, [[MIDRESULT1]], [[MIDRESULT2]]
183 ; GCN: buffer_store_dword [[RESULT]],
/external/toolchain-utils/crosperf/test_cache/test_input/
Dresults.txt1 …RESULT 3d-cube: 3d-cube= [28,28,28,28,31,26,28,28,28,27] ms\n13:23:35 INFO | autoserv| Avg 3d-cube…
/external/python/cpython3/Misc/
Dpython-config.sh.in18 RESULT=$(dirname $(cd $(dirname "$1") && pwd -P))
20 if readlink -f "$RESULT" >/dev/null 2>&1; then
21 RESULT=$(readlink -f "$RESULT")
24 echo $RESULT
/external/ltp/tools/pounder21/
Dnfs_logging68 RESULT=$?
70 if [ $RESULT -gt 0 ]; then
86 RESULT=$?
88 if [ $RESULT -gt 0 ]; then
/external/ltp/tools/pounder21/src/
Dlibidecd.sh73 RESULT=$?
75 if [ $RESULT -eq 0 ]; then
85 RESULT=$?
87 if [ $RESULT -eq 0 ]; then
/external/pdfium/testing/tools/
Dmake_expected.sh15 for RESULT in $RESULTS ; do
16 EXPECTED=`echo -n $RESULT | sed 's/[.]pdf[.]/_expected.pdf./'`
17 mv $RESULT $EXPECTED
/external/ltp/testcases/kernel/fs/fsx-linux/
Dfsxtest40 RESULT=$?
42 if [ $RESULT -eq "0" ]; then
50 exit $RESULT
Dfsxtest0236 RESULT=$?
38 if [ $RESULT -eq "0" ]; then
44 exit $RESULT
/external/ltp/testcases/network/nfsv4/locks/
Dlocktests.c691 state = RESULT; in master()
702 state = RESULT; in master()
707 case RESULT: in master()
787 state = RESULT; in slave()
798 state = RESULT; in slave()
806 state = RESULT; in slave()
816 state = RESULT; in slave()
826 state = RESULT; in slave()
845 state = RESULT; in slave()
853 state = RESULT; in slave()
[all …]

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