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Searched refs:RH (Results 1 – 25 of 190) sorted by relevance

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/external/swiftshader/third_party/LLVM/test/CodeGen/Generic/
Di128-addsub.ll3 define void @test_add(i64 %AL, i64 %AH, i64 %BL, i64 %BH, i64* %RL, i64* %RH) {
18 store i64 %tmp2122, i64* %RH
22 define void @test_sub(i64 %AL, i64 %AH, i64 %BL, i64 %BH, i64* %RL, i64* %RH) {
37 store i64 %tmp2122, i64* %RH
/external/llvm/test/CodeGen/Generic/
Di128-addsub.ll3 define void @test_add(i64 %AL, i64 %AH, i64 %BL, i64 %BH, i64* %RL, i64* %RH) {
18 store i64 %tmp2122, i64* %RH
22 define void @test_sub(i64 %AL, i64 %AH, i64 %BL, i64 %BH, i64* %RL, i64* %RH) {
37 store i64 %tmp2122, i64* %RH
/external/swiftshader/third_party/LLVM/test/CodeGen/Blackfin/
Daddsub-i128.ll6 define void @test_add(i64 %AL, i64 %AH, i64 %BL, i64 %BH, i64* %RL, i64* %RH) {
21 store i64 %tmp2122, i64* %RH
25 define void @test_sub(i64 %AL, i64 %AH, i64 %BL, i64 %BH, i64* %RL, i64* %RH) {
40 store i64 %tmp2122, i64* %RH
/external/llvm/test/CodeGen/Hexagon/
Dsube.ll12 define void @check_sube_subc(i64 %AL, i64 %AH, i64 %BL, i64 %BH, i64* %RL, i64* %RH) {
27 store i64 %tmp2122, i64* %RH
Dadde.ll17 define void @check_adde_addc (i64 %AL, i64 %AH, i64 %BL, i64 %BH, i64* %RL, i64* %RH) {
32 store i64 %tmp2122, i64* %RH
/external/strace/
DChangeLog-CVS296 Fixes RH#471169 "format fcntl64() system calls for
361 Fixes RH#472053.
399 Fixes RH#470529.
463 Fixes RH#105371.
552 Fixes RH#455078.
571 Fixes RH#457291.
620 Fixes RH#448628.
634 Fixes RH#448629.
638 Fixes RH#455821.
682 Fixes RH#453438.
[all …]
/external/swiftshader/third_party/LLVM/lib/CodeGen/SelectionDAG/
DLegalizeTypesGeneric.cpp442 SDValue LL, LH, RL, RH, CL, CH; in SplitRes_SELECT() local
445 GetSplitOp(N->getOperand(2), RL, RH); in SplitRes_SELECT()
461 Hi = DAG.getNode(N->getOpcode(), dl, LH.getValueType(), CH, LH, RH); in SplitRes_SELECT()
466 SDValue LL, LH, RL, RH; in SplitRes_SELECT_CC() local
469 GetSplitOp(N->getOperand(3), RL, RH); in SplitRes_SELECT_CC()
474 N->getOperand(1), LH, RH, N->getOperand(4)); in SplitRes_SELECT_CC()
DLegalizeIntegerTypes.cpp1881 SDValue LL, LH, RL, RH; in ExpandIntRes_Logical() local
1883 GetExpandedInteger(N->getOperand(1), RL, RH); in ExpandIntRes_Logical()
1885 Hi = DAG.getNode(N->getOpcode(), dl, LL.getValueType(), LH, RH); in ExpandIntRes_Logical()
1899 SDValue LL, LH, RL, RH; in ExpandIntRes_MUL() local
1901 GetExpandedInteger(N->getOperand(1), RL, RH); in ExpandIntRes_MUL()
1945 RH = DAG.getNode(ISD::MUL, dl, NVT, LL, RH); in ExpandIntRes_MUL()
1947 Hi = DAG.getNode(ISD::ADD, dl, NVT, Hi, RH); in ExpandIntRes_MUL()
1954 RH = DAG.getNode(ISD::MUL, dl, NVT, LL, RH); in ExpandIntRes_MUL()
1956 Hi = DAG.getNode(ISD::ADD, dl, NVT, Hi, RH); in ExpandIntRes_MUL()
/external/llvm/lib/CodeGen/SelectionDAG/
DLegalizeTypesGeneric.cpp525 SDValue LL, LH, RL, RH, CL, CH; in SplitRes_SELECT() local
528 GetSplitOp(N->getOperand(2), RL, RH); in SplitRes_SELECT()
542 Hi = DAG.getNode(N->getOpcode(), dl, LH.getValueType(), CH, LH, RH); in SplitRes_SELECT()
547 SDValue LL, LH, RL, RH; in SplitRes_SELECT_CC() local
550 GetSplitOp(N->getOperand(3), RL, RH); in SplitRes_SELECT_CC()
555 N->getOperand(1), LH, RH, N->getOperand(4)); in SplitRes_SELECT_CC()
DTargetLowering.cpp2982 SDValue RL, SDValue RH) const { in expandMUL()
2997 assert((LL.getNode() && LH.getNode() && RL.getNode() && RH.getNode()) || in expandMUL()
2998 (!LL.getNode() && !LH.getNode() && !RL.getNode() && !RH.getNode())); in expandMUL()
3044 if (!LH.getNode() && !RH.getNode() && in expandMUL()
3052 RH = DAG.getNode(ISD::SRL, dl, VT, N->getOperand(1), Shift); in expandMUL()
3053 RH = DAG.getNode(ISD::TRUNCATE, dl, HiLoVT, RH); in expandMUL()
3065 RH = DAG.getNode(ISD::MUL, dl, HiLoVT, LL, RH); in expandMUL()
3067 Hi = DAG.getNode(ISD::ADD, dl, HiLoVT, Hi, RH); in expandMUL()
3074 RH = DAG.getNode(ISD::MUL, dl, HiLoVT, LL, RH); in expandMUL()
3076 Hi = DAG.getNode(ISD::ADD, dl, HiLoVT, Hi, RH); in expandMUL()
/external/honggfuzz/examples/apache-httpd/corpus_http2/
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/external/honggfuzz/examples/apache-httpd/corpus_http1/
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/external/icu/icu4c/source/data/coll/
Dcy.txt14 "&R<rh<<<Rh<<<RH"
/external/llvm/lib/Target/Hexagon/
DHexagonBitSimplify.cpp1614 BitTracker::RegisterRef RH = MI.getOperand(1), RL = MI.getOperand(2); in propagateRegCopy() local
1618 RH.Reg, RH.Sub, MRI); in propagateRegCopy()
1671 unsigned B, RegHalf &RH);
1701 const BitTracker::RegisterCell &RC, unsigned B, RegHalf &RH) { in matchHalf() argument
1768 RH.Reg = Reg; in matchHalf()
1769 RH.Sub = Sub; in matchHalf()
1770 RH.Low = Low; in matchHalf()
1772 if (!HBS::getFinalVRegClass(RH, MRI)) in matchHalf()
1773 RH.Sub = 0; in matchHalf()
/external/python/cpython2/Demo/tix/
DINSTALL.txt7 Tix.py has been written and tested on an Intel Pentium running RH Linux 5.2
/external/swiftshader/third_party/LLVM/lib/Target/XCore/
DXCoreISelLowering.cpp688 SDValue LH, RH; in TryExpandADDWithMul() local
691 RH = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, in TryExpandADDWithMul()
697 RH = DAG.getNode(ISD::MUL, dl, MVT::i32, LL, RH); in TryExpandADDWithMul()
699 Hi = DAG.getNode(ISD::ADD, dl, MVT::i32, Hi, RH); in TryExpandADDWithMul()
/external/icu/icu4c/source/data/translit/
DGrek_Latn.txt180 Ρ $rough ↔ RH ;
/external/llvm/lib/Target/XCore/
DXCoreISelLowering.cpp701 SDValue LH, RH; in TryExpandADDWithMul() local
704 RH = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, in TryExpandADDWithMul()
710 RH = DAG.getNode(ISD::MUL, dl, MVT::i32, LL, RH); in TryExpandADDWithMul()
712 Hi = DAG.getNode(ISD::ADD, dl, MVT::i32, Hi, RH); in TryExpandADDWithMul()
/external/v8/src/arm64/
Dconstants-arm64.h775 V(ST, RH, w, 0x40000000), \
779 V(LD, RH, w, 0x40400000), \
/external/deqp/framework/common/
DtcuCompressedTexture.cpp674 const deUint8 RH = extend6To8((deUint8)((RH1 << 1) | RH2)); in decompressETC2Block() local
687 const int unclampedR = (x * ((int)RH-(int)RO) + y * ((int)RV-(int)RO) + 4*(int)RO + 2) >> 2; in decompressETC2Block()

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