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Searched refs:RSI (Results 1 – 25 of 66) sorted by relevance

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/external/llvm/lib/Target/AMDGPU/
DR600OptimizeVectorRegisters.cpp81 bool operator==(const RegSeqInfo &RSI) const { in operator ==()
82 return RSI.Instr == Instr; in operator ==()
96 bool tryMergeUsingCommonSlot(RegSeqInfo &RSI, RegSeqInfo &CompatibleRSI,
98 bool tryMergeUsingFreeSlot(RegSeqInfo &RSI, RegSeqInfo &CompatibleRSI,
104 void trackRSI(const RegSeqInfo &RSI);
180 RegSeqInfo *RSI, const RegSeqInfo *BaseRSI, in RebuildVector() argument
182 unsigned Reg = RSI->Instr->getOperand(0).getReg(); in RebuildVector()
183 MachineBasicBlock::iterator Pos = RSI->Instr; in RebuildVector()
190 for (DenseMap<unsigned, unsigned>::iterator It = RSI->RegToChan.begin(), in RebuildVector()
191 E = RSI->RegToChan.end(); It != E; ++It) { in RebuildVector()
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/external/llvm/test/CodeGen/X86/
Dor-lea.ll12 ; CHECK-NEXT: # kill: %ESI<def> %ESI<kill> %RSI<def>
27 ; CHECK-NEXT: # kill: %ESI<def> %ESI<kill> %RSI<def>
42 ; CHECK-NEXT: # kill: %ESI<def> %ESI<kill> %RSI<def>
57 ; CHECK-NEXT: # kill: %ESI<def> %ESI<kill> %RSI<def>
72 ; CHECK-NEXT: # kill: %ESI<def> %ESI<kill> %RSI<def>
89 ; CHECK-NEXT: # kill: %ESI<def> %ESI<kill> %RSI<def>
Dvector-shuffle-variable-128.ll205 ; SSE2-NEXT: # kill: %ESI<def> %ESI<kill> %RSI<def>
247 ; SSSE3-NEXT: # kill: %ESI<def> %ESI<kill> %RSI<def>
290 ; SSE41-NEXT: # kill: %ESI<def> %ESI<kill> %RSI<def>
323 ; AVX-NEXT: # kill: %ESI<def> %ESI<kill> %RSI<def>
374 ; SSE2-NEXT: # kill: %ESI<def> %ESI<kill> %RSI<def>
449 ; SSSE3-NEXT: # kill: %ESI<def> %ESI<kill> %RSI<def>
530 ; SSE41-NEXT: # kill: %ESI<def> %ESI<kill> %RSI<def>
597 ; AVX-NEXT: # kill: %ESI<def> %ESI<kill> %RSI<def>
1152 ; SSE2-NEXT: # kill: %ESI<def> %ESI<kill> %RSI<def>
1191 ; SSSE3-NEXT: # kill: %ESI<def> %ESI<kill> %RSI<def>
[all …]
/external/llvm/lib/Target/X86/MCTargetDesc/
DX86MCTargetDesc.cpp109 X86::RCX, X86::RDX, X86::RSI, X86::RDI, X86::RBP, X86::RSP, in initLLVMToSEHAndCVRegMapping()
285 case X86::SIL: case X86::SI: case X86::ESI: case X86::RSI: in getX86SubSuperRegisterOrZero()
313 case X86::SIL: case X86::SI: case X86::ESI: case X86::RSI: in getX86SubSuperRegisterOrZero()
350 case X86::SIL: case X86::SI: case X86::ESI: case X86::RSI: in getX86SubSuperRegisterOrZero()
386 case X86::SIL: case X86::SI: case X86::ESI: case X86::RSI: in getX86SubSuperRegisterOrZero()
422 case X86::SIL: case X86::SI: case X86::ESI: case X86::RSI: in getX86SubSuperRegisterOrZero()
423 return X86::RSI; in getX86SubSuperRegisterOrZero()
/external/libunwind/src/x86_64/
Dinit.h53 c->dwarf.loc[RSI] = REG_INIT_LOC(c, rsi, RSI); in common_init()
Dunwind_i.h43 #define RSI 4 macro
DGregs.c111 case UNW_X86_64_RSI: loc = c->dwarf.loc[RSI]; break; in tdep_access_reg()
/external/llvm/lib/Target/X86/
DX86CallingConv.td233 CCIfType<[i64], CCAssignToReg<[RBX, RBP, RDI, RSI, RDX, RCX, R8, R9,
312 CCIfType<[i64], CCAssignToReg<[RDI, RSI, RDX, RCX, R8 , R9 ]>>,
374 RDI, RSI, RDX, RCX, R8, R9,
463 CCAssignToReg<[R13, RBP, R12, RBX, R14, RSI, RDI, R8, R9, R15]>>,
476 CCIfType<[i64], CCAssignToReg<[R15, RBP, RSI, RDX, RCX, R8]>>,
769 CCIfType<[i64], CCIfSubtarget<"is64Bit()", CCAssignToReg<[RDI, RSI, RDX, RCX]>>>,
863 def CSR_Win64 : CalleeSavedRegs<(add RBX, RBP, RDI, RSI, R12, R13, R14, R15,
869 def CSR_64_TLS_Darwin : CalleeSavedRegs<(add CSR_64, RCX, RDX, RSI,
879 def CSR_64_RT_MostRegs : CalleeSavedRegs<(add CSR_64, RAX, RCX, RDX, RSI, RDI,
888 def CSR_64_MostRegs : CalleeSavedRegs<(add RBX, RCX, RDX, RSI, RDI, R8, R9, R10,
[all …]
DX86SelectionDAGInfo.cpp224 const MCPhysReg ClobberSet[] = {X86::RCX, X86::RSI, X86::RDI, in EmitTargetCodeForMemcpy()
253 Chain = DAG.getCopyToReg(Chain, dl, Subtarget.is64Bit() ? X86::RSI : X86::ESI, in EmitTargetCodeForMemcpy()
DX86InstrSystem.td542 let Defs = [RSI, RDI], Uses = [RBX, RDX, RSI, RDI] in {
550 let Defs = [RAX, RSI, RDI], Uses = [RAX, RSI, RDI] in {
554 let Defs = [RAX, RDX, RSI], Uses = [RAX, RSI] in
/external/strace/linux/x86_64/
Duserent.h14 XLAT(8*RSI),
/external/llvm/utils/TableGen/
DCodeGenSchedule.cpp1042 RSI = PTI->ReadSequences.begin(), RSE = PTI->ReadSequences.end(); in hasVariant() local
1043 RSI != RSE; ++RSI) { in hasVariant()
1045 RI = RSI->begin(), RE = RSI->end(); RI != RE; ++RI) { in hasVariant()
1279 RSI = Trans.ReadSequences.begin(), RSE = Trans.ReadSequences.end(); in substituteVariants() local
1280 RSI != RSE; ++RSI) { in substituteVariants()
1286 substituteVariantOperand(*RSI, /*IsRead=*/true, StartIdx); in substituteVariants()
1308 RSI = I->ReadSequences.begin(), RSE = I->ReadSequences.end(); in inferFromTransitions() local
1309 RSI != RSE; ++RSI) { in inferFromTransitions()
1312 SchedModels.findOrInsertRW(*RSI, /*IsRead=*/true)); in inferFromTransitions()
/external/kernel-headers/original/uapi/asm-x86/asm/
Dptrace-abi.h47 #define RSI 104 macro
/external/valgrind/coregrind/m_sigframe/
Dsigframe-amd64-darwin.c102 SC2(__rsi,RSI); in synthesize_ucontext()
130 SC2(RSI,__rsi); in restore_from_ucontext()
/external/swiftshader/third_party/LLVM/lib/Target/X86/
DX86RegisterInfo.cpp370 X86::RBX, X86::RBP, X86::RDI, X86::RSI, in getCalleeSavedRegs()
689 case X86::SIL: case X86::SI: case X86::ESI: case X86::RSI: in getX86SubSuperRegister()
726 case X86::SIL: case X86::SI: case X86::ESI: case X86::RSI: in getX86SubSuperRegister()
762 case X86::SIL: case X86::SI: case X86::ESI: case X86::RSI: in getX86SubSuperRegister()
798 case X86::SIL: case X86::SI: case X86::ESI: case X86::RSI: in getX86SubSuperRegister()
799 return X86::RSI; in getX86SubSuperRegister()
DX86InstrSystem.td433 let Defs = [RSI, RDI], Uses = [RBX, RDX, RSI, RDI] in {
441 let Defs = [RAX, RSI, RDI], Uses = [RAX, RSI, RDI] in {
445 let Defs = [RAX, RDX, RSI], Uses = [RAX, RSI] in
DX86RegisterInfo.td128 def RSI : RegisterWithSubRegs<"rsi", [ESI]>, DwarfRegNum<[4, -2, -2]>;
313 (add RAX, RCX, RDX, RSI, RDI, R8, R9, R10, R11,
356 def GR64_TC : RegisterClass<"X86", [i64], 64, (add RAX, RCX, RDX, RSI, RDI,
387 (add RAX, RCX, RDX, RSI, RDI, RBX, RBP, RSP, RIP)> {
DX86GenRegisterInfo.inc132 RSI = 113,
301 const unsigned ESI_Overlaps[] = { X86::ESI, X86::RSI, X86::SI, X86::SIL, 0 };
361 const unsigned RSI_Overlaps[] = { X86::RSI, X86::ESI, X86::SI, X86::SIL, 0 };
363 const unsigned SI_Overlaps[] = { X86::SI, X86::ESI, X86::RSI, X86::SIL, 0 };
364 const unsigned SIL_Overlaps[] = { X86::SIL, X86::ESI, X86::RSI, X86::SI, 0 };
515 const unsigned ESI_SuperRegsSet[] = { X86::RSI, 0 };
542 const unsigned SI_SuperRegsSet[] = { X86::ESI, X86::RSI, 0 };
543 const unsigned SIL_SuperRegsSet[] = { X86::SI, X86::ESI, X86::RSI, 0 };
678 { "RSI", RSI_Overlaps, RSI_SubRegsSet, Empty_SuperRegsSet },
740 …X86::RAX, X86::RCX, X86::RDX, X86::RSI, X86::RDI, X86::R8, X86::R9, X86::R10, X86::R11, X86::RBX, …
[all …]
/external/llvm/test/tools/llvm-objdump/
Dwin64-unwind-data.test22 OBJ-NEXT: 0x09: UOP_SaveNonVol RSI [0x0010]
71 EXE-NEXT: 0x09: UOP_SaveNonVol RSI [0x0010]
/external/swiftshader/third_party/LLVM/lib/Target/X86/Disassembler/
DX86DisassemblerDecoder.h167 ENTRY(RSI) \
185 ENTRY(RSI) \
/external/lzma/Asm/x86/
D7zAsm.asm72 r6 equ RSI
/external/llvm/lib/Target/X86/Disassembler/
DX86DisassemblerDecoder.h177 ENTRY(RSI) \
195 ENTRY(RSI) \
/external/capstone/arch/X86/
DX86DisassemblerDecoder.h190 ENTRY(RSI) \
208 ENTRY(RSI) \
/external/google-breakpad/src/common/android/
Dbreakpad_getcontext_unittest.cc130 CHECK_REG(RSI); in TEST()
/external/swiftshader/third_party/LLVM/test/CodeGen/X86/
Dghc-cc64.ll10 @r3 = external global i64 ; assigned to register: RSI

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