| /external/vulkan-validation-layers/libs/glm/detail/ |
| D | intrinsic_integer.inl | 41 __m128i Reg2; local
50 Reg2 = _mm_slli_si128(Reg1, 2);
51 Reg1 = _mm_or_si128(Reg2, Reg1);
56 Reg2 = _mm_slli_si128(Reg1, 1);
57 Reg1 = _mm_or_si128(Reg2, Reg1);
62 Reg2 = _mm_slli_epi32(Reg1, 4);
63 Reg1 = _mm_or_si128(Reg2, Reg1);
68 Reg2 = _mm_slli_epi32(Reg1, 2);
69 Reg1 = _mm_or_si128(Reg2, Reg1);
74 Reg2 = _mm_slli_epi32(Reg1, 1);
[all …]
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| /external/llvm/lib/Target/AArch64/MCTargetDesc/ |
| D | AArch64AsmBackend.cpp | 454 unsigned Reg2 = MRI.getLLVMRegNum(Inst2.getRegister(), true); in generateCompactUnwindEncoding() local
465 Reg2 = getXRegFromWReg(Reg2); in generateCompactUnwindEncoding()
467 if (Reg1 == AArch64::X19 && Reg2 == AArch64::X20 && in generateCompactUnwindEncoding()
470 else if (Reg1 == AArch64::X21 && Reg2 == AArch64::X22 && in generateCompactUnwindEncoding()
473 else if (Reg1 == AArch64::X23 && Reg2 == AArch64::X24 && in generateCompactUnwindEncoding()
476 else if (Reg1 == AArch64::X25 && Reg2 == AArch64::X26 && in generateCompactUnwindEncoding()
479 else if (Reg1 == AArch64::X27 && Reg2 == AArch64::X28 && in generateCompactUnwindEncoding()
484 Reg2 = getDRegFromBReg(Reg2); in generateCompactUnwindEncoding()
490 if (Reg1 == AArch64::D8 && Reg2 == AArch64::D9 && in generateCompactUnwindEncoding()
493 else if (Reg1 == AArch64::D10 && Reg2 == AArch64::D11 && in generateCompactUnwindEncoding()
[all …]
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| /external/llvm/lib/Target/AArch64/ |
| D | AArch64FrameLowering.cpp | 874 RegPairInfo() : Reg1(AArch64::NoRegister), Reg2(AArch64::NoRegister) {} in RegPairInfo()
876 unsigned Reg2; member
880 bool isPaired() const { return Reg2 != AArch64::NoRegister; } in isPaired()
916 RPI.Reg2 = NextReg; in computeCalleeSaveRegisterPairs()
934 ((RPI.Reg1 == AArch64::LR && RPI.Reg2 == AArch64::FP) || in computeCalleeSaveRegisterPairs()
935 RPI.Reg1 + 1 == RPI.Reg2))) && in computeCalleeSaveRegisterPairs()
975 unsigned Reg2 = RPI.Reg2; in spillCalleeSavedRegisters() local
994 dbgs() << ", " << TRI->getName(Reg2); in spillCalleeSavedRegisters()
1003 MBB.addLiveIn(Reg2); in spillCalleeSavedRegisters()
1004 MIB.addReg(Reg2, getPrologueDeath(MF, Reg2)); in spillCalleeSavedRegisters()
[all …]
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| /external/llvm/lib/Target/Mips/ |
| D | MipsAsmPrinter.h | 73 unsigned Reg1, unsigned Reg2);
76 unsigned Reg1, unsigned Reg2, unsigned Reg3);
79 unsigned Reg1, unsigned Reg2, unsigned FPReg1,
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| D | MipsAsmPrinter.cpp | 770 unsigned Reg2) { in EmitInstrRegReg() argument
779 Reg1 = Reg2; in EmitInstrRegReg()
780 Reg2 = Temp; in EmitInstrRegReg()
784 I.addOperand(MCOperand::createReg(Reg2)); in EmitInstrRegReg()
790 unsigned Reg2, unsigned Reg3) { in EmitInstrRegRegReg() argument
794 I.addOperand(MCOperand::createReg(Reg2)); in EmitInstrRegRegReg()
801 unsigned Reg2, unsigned FPReg1, in EmitMovFPIntPair() argument
805 Reg1 = Reg2; in EmitMovFPIntPair()
806 Reg2 = temp; in EmitMovFPIntPair()
809 EmitInstrRegReg(STI, MovOpc, Reg2, FPReg2); in EmitMovFPIntPair()
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| D | Mips16InstrInfo.cpp | 263 unsigned Reg1, unsigned Reg2) const { in adjustStackPtrBig()
274 MachineInstrBuilder MIB2 = BuildMI(MBB, I, DL, get(Mips::MoveR3216), Reg2); in adjustStackPtrBig()
278 MIB3.addReg(Reg2, RegState::Kill); in adjustStackPtrBig()
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| D | Mips16InstrInfo.h | 115 unsigned Reg1, unsigned Reg2) const;
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| /external/swiftshader/third_party/LLVM/lib/CodeGen/ |
| D | TargetInstrInfoImpl.cpp | 79 unsigned Reg2 = MI->getOperand(Idx2).getReg(); in commuteInstruction() local
87 Reg0 = Reg2; in commuteInstruction()
88 } else if (HasDef && Reg0 == Reg2 && in commuteInstruction()
101 .addReg(Reg2, getKillRegState(Reg2IsKill)) in commuteInstruction()
105 .addReg(Reg2, getKillRegState(Reg2IsKill)) in commuteInstruction()
112 MI->getOperand(Idx1).setReg(Reg2); in commuteInstruction()
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| D | AggressiveAntiDepBreaker.h | 104 unsigned UnionGroups(unsigned Reg1, unsigned Reg2);
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| /external/llvm/test/CodeGen/Hexagon/ |
| D | newvaluejump2.ll | 10 %Reg2 = alloca i32, align 4
11 %0 = load i32, i32* %Reg2, align 4
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| /external/swiftshader/third_party/LLVM/lib/Target/SystemZ/ |
| D | SystemZInstrBuilder.h | 84 unsigned Reg1, bool isKill1, unsigned Reg2, bool isKill2) { in addRegReg() argument
86 .addReg(Reg2, getKillRegState(isKill2)); in addRegReg()
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| /external/swiftshader/third_party/LLVM/utils/TableGen/ |
| D | CodeGenRegisters.cpp | 620 CodeGenRegister *Reg2 = i1->second; in computeComposites() local
622 if (Reg1 == Reg2) in computeComposites()
624 const CodeGenRegister::SubRegMap &SRM2 = Reg2->getSubRegs(); in computeComposites()
631 if (Reg2 == Reg3) in computeComposites()
714 CodeGenRegister *Reg2 = getReg(RegList[i2]); in computeOverlaps() local
715 CodeGenRegister::Set &Overlaps2 = Map[Reg2]; in computeOverlaps()
716 const CodeGenRegister::SuperRegList &Supers2 = Reg2->getSuperRegs(); in computeOverlaps()
718 Overlaps.insert(Reg2); in computeOverlaps()
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| /external/llvm/lib/Target/PowerPC/ |
| D | PPCVSXFMAMutate.cpp | 189 unsigned Reg2 = MI->getOperand(2).getReg(); in processBlock() local
191 if (LIS->getInterval(Reg2).Query(FMAIdx).isKill() in processBlock()
192 && Reg2 != OldFMAReg) { in processBlock()
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| /external/swiftshader/third_party/LLVM/lib/Target/X86/ |
| D | X86InstrBuilder.h | 117 unsigned Reg2, bool isKill2) { in addRegReg() argument
119 .addReg(Reg2, getKillRegState(isKill2)).addImm(0).addReg(0); in addRegReg()
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| /external/swiftshader/third_party/LLVM/include/llvm/MC/ |
| D | MCRegisterInfo.h | 85 bool contains(unsigned Reg1, unsigned Reg2) const { in contains() argument
86 return contains(Reg1) && contains(Reg2); in contains()
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| /external/llvm/lib/Target/X86/ |
| D | X86InstrBuilder.h | 145 unsigned Reg2, bool isKill2) { in addRegReg() argument
147 .addReg(Reg2, getKillRegState(isKill2)).addImm(0).addReg(0); in addRegReg()
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| /external/swiftshader/third_party/LLVM/lib/Target/PowerPC/ |
| D | PPCInstrInfo.cpp | 119 unsigned Reg2 = MI->getOperand(2).getReg(); in commuteInstruction() local
139 unsigned Reg0 = ChangeReg0 ? Reg2 : MI->getOperand(0).getReg(); in commuteInstruction()
143 .addReg(Reg2, getKillRegState(Reg2IsKill)) in commuteInstruction()
150 MI->getOperand(0).setReg(Reg2); in commuteInstruction()
152 MI->getOperand(1).setReg(Reg2); in commuteInstruction()
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| /external/swiftshader/third_party/LLVM/include/llvm/Target/ |
| D | TargetRegisterInfo.h | 86 bool contains(unsigned Reg1, unsigned Reg2) const { in contains() argument
87 return MC->contains(Reg1, Reg2); in contains()
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| /external/llvm/lib/Target/ARM/ |
| D | Thumb2SizeReduction.cpp | 710 unsigned Reg2 = MI->getOperand(2).getReg(); in ReduceTo2Addr() local
713 || !isARMLowRegister(Reg2)) in ReduceTo2Addr()
715 if (Reg0 != Reg2) { in ReduceTo2Addr()
745 unsigned Reg2 = MI->getOperand(2).getReg(); in ReduceTo2Addr() local
746 if (Entry.LowRegs2 && !isARMLowRegister(Reg2)) in ReduceTo2Addr()
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| D | A15SDOptimizer.cpp | 86 unsigned Reg2);
461 const DebugLoc &DL, unsigned Reg1, unsigned Reg2) { in createRegSequence() argument
469 .addReg(Reg2) in createRegSequence()
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| /external/llvm/lib/Target/Hexagon/AsmParser/ |
| D | HexagonAsmParser.cpp | 1607 StringRef Reg2(R2); in processInstruction() local
1608 Inst.addOperand(MCOperand::createReg(matchRegister(Reg2))); in processInstruction()
1622 StringRef Reg2(R2); in processInstruction() local
1623 Inst.addOperand(MCOperand::createReg(matchRegister(Reg2))); in processInstruction()
1638 StringRef Reg2(R2); in processInstruction() local
1639 Inst.addOperand(MCOperand::createReg(matchRegister(Reg2))); in processInstruction()
1978 StringRef Reg2(R2); in processInstruction() local
1982 TmpInst.addOperand(MCOperand::createReg(matchRegister(Reg2))); in processInstruction()
2132 StringRef Reg2(R2); in processInstruction() local
2136 TmpInst.addOperand(MCOperand::createReg(matchRegister(Reg2))); in processInstruction()
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| /external/llvm/lib/CodeGen/ |
| D | AggressiveAntiDepBreaker.h | 100 unsigned UnionGroups(unsigned Reg1, unsigned Reg2);
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| D | TargetInstrInfo.cpp | 145 unsigned Reg2 = MI.getOperand(Idx2).getReg(); in commuteInstructionImpl() local
160 Reg0 = Reg2; in commuteInstructionImpl()
162 } else if (HasDef && Reg0 == Reg2 && in commuteInstructionImpl()
183 CommutedMI->getOperand(Idx1).setReg(Reg2); in commuteInstructionImpl()
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| /external/llvm/include/llvm/MC/ |
| D | MCRegisterInfo.h | 76 bool contains(unsigned Reg1, unsigned Reg2) const { in contains() argument
77 return contains(Reg1) && contains(Reg2); in contains()
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| /external/llvm/include/llvm/Target/ |
| D | TargetRegisterInfo.h | 102 bool contains(unsigned Reg1, unsigned Reg2) const { in contains() argument
103 return MC->contains(Reg1, Reg2); in contains()
|