Searched refs:RegLimit (Results 1 – 6 of 6) sorted by relevance
| /external/llvm/lib/CodeGen/SelectionDAG/ |
| D | ResourcePriorityQueue.cpp | 56 RegLimit.resize(NumRC); in ResourcePriorityQueue()
58 std::fill(RegLimit.begin(), RegLimit.end(), 0); in ResourcePriorityQueue()
63 RegLimit[(*I)->getID()] = TRI->getRegPressureLimit(*I, *IS->MF); in ResourcePriorityQueue()
380 rawRegPressureDelta(SU, RC->getID()) >= RegLimit[RC->getID()])) in regPressureDelta()
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| D | ScheduleDAGRRList.cpp | 1643 std::vector<unsigned> RegLimit; member in __anon0bb2ca0d0211::RegReductionPQBase
1658 RegLimit.resize(NumRC); in RegReductionPQBase()
1660 std::fill(RegLimit.begin(), RegLimit.end(), 0); in RegReductionPQBase()
1664 RegLimit[(*I)->getID()] = tri->getRegPressureLimit(*I, MF); in RegReductionPQBase()
1937 << RegLimit[Id] << '\n'); in dumpRegPressure()
1960 if ((RegPressure[RCId] + Cost) >= RegLimit[RCId]) in HighRegPressure()
1979 if (RegPressure[RCId] >= RegLimit[RCId]) in MayReduceRegPressure()
2010 if (RegPressure[RCId] >= RegLimit[RCId]) in RegPressureDiff()
2025 if (RegPressure[RCId] >= RegLimit[RCId]) in RegPressureDiff()
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| /external/swiftshader/third_party/LLVM/lib/CodeGen/ |
| D | MachineLICM.cpp | 92 SmallVector<unsigned, 8> RegLimit; member in __anon6241b0590111::MachineLICM
139 RegLimit.clear(); in releaseMemory()
329 RegLimit.resize(NumRC); in runOnMachineFunction()
332 RegLimit[(*I)->getID()] = TRI->getRegPressureLimit(*I, MF); in runOnMachineFunction()
942 if (RP[RCId] + CI->second >= RegLimit[RCId]) in CanCauseHighRegPressure()
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| /external/llvm/lib/CodeGen/ |
| D | MachineLICM.cpp | 105 SmallVector<unsigned, 8> RegLimit; member in __anon4fee4dad0111::MachineLICM
150 RegLimit.clear(); in releaseMemory()
288 RegLimit.resize(NumRPS); in runOnMachineFunction()
290 RegLimit[i] = TRI->getRegPressureSetLimit(MF, i); in runOnMachineFunction()
1030 int Limit = RegLimit[Class]; in CanCauseHighRegPressure()
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| /external/llvm/include/llvm/CodeGen/ |
| D | ResourcePriorityQueue.h | 57 std::vector<unsigned> RegLimit; variable
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| /external/swiftshader/third_party/LLVM/lib/CodeGen/SelectionDAG/ |
| D | ScheduleDAGRRList.cpp | 1532 std::vector<unsigned> RegLimit; member in __anon113a15390411::RegReductionPQBase
1546 RegLimit.resize(NumRC); in RegReductionPQBase()
1548 std::fill(RegLimit.begin(), RegLimit.end(), 0); in RegReductionPQBase()
1552 RegLimit[(*I)->getID()] = tri->getRegPressureLimit(*I, MF); in RegReductionPQBase()
1826 DEBUG(dbgs() << RC->getName() << ": " << RP << " / " << RegLimit[Id] in dumpRegPressure()
1850 if ((RegPressure[RCId] + Cost) >= RegLimit[RCId]) in HighRegPressure()
1869 if (RegPressure[RCId] >= RegLimit[RCId]) in MayReduceRegPressure()
1901 if (RegPressure[RCId] >= RegLimit[RCId]) in RegPressureDiff()
1916 if (RegPressure[RCId] >= RegLimit[RCId]) in RegPressureDiff()
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