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Searched refs:RegNum (Results 1 – 25 of 61) sorted by relevance

123

/external/swiftshader/third_party/subzero/src/
DIceRegistersMIPS32.h68 static inline GPRRegister getEncodedGPR(RegNumT RegNum) { in getEncodedGPR() argument
69 assert(int(Reg_GPR_First) <= int(RegNum)); in getEncodedGPR()
70 assert(unsigned(RegNum) <= Reg_GPR_Last); in getEncodedGPR()
71 return GPRRegister(RegNum - Reg_GPR_First); in getEncodedGPR()
74 static inline bool isGPRReg(RegNumT RegNum) { in isGPRReg() argument
75 bool IsGPR = ((int(Reg_GPR_First) <= int(RegNum)) && in isGPRReg()
76 (unsigned(RegNum) <= Reg_GPR_Last)) || in isGPRReg()
77 ((int(Reg_I64PAIR_First) <= int(RegNum)) && in isGPRReg()
78 (unsigned(RegNum) <= Reg_I64PAIR_Last)); in isGPRReg()
82 static inline FPRRegister getEncodedFPR(RegNumT RegNum) { in getEncodedFPR() argument
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DIceRegistersARM32.h105 static inline void assertValidRegNum(RegNumT RegNum) { in assertValidRegNum() argument
106 (void)RegNum; in assertValidRegNum()
107 assert(RegNum.hasValue()); in assertValidRegNum()
110 static inline bool isGPRegister(RegNumT RegNum) { in isGPRegister() argument
111 RegNum.assertIsValid(); in isGPRegister()
112 return RegTable[RegNum].IsGPR; in isGPRegister()
125 static inline GPRRegister getEncodedGPR(RegNumT RegNum) { in getEncodedGPR() argument
126 RegNum.assertIsValid(); in getEncodedGPR()
127 return GPRRegister(RegTable[RegNum].Encoding); in getEncodedGPR()
140 static inline bool isGPR(RegNumT RegNum) { in isGPR() argument
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DIceTargetLoweringX8664Traits.h304 static const char *getRegName(RegNumT RegNum) { in getRegName()
313 RegNum.assertIsValid(); in getRegName()
314 return RegNames[RegNum]; in getRegName()
317 static GPRRegister getEncodedGPR(RegNumT RegNum) { in getEncodedGPR()
326 RegNum.assertIsValid(); in getEncodedGPR()
327 assert(GPRRegs[RegNum] != GPRRegister::Encoded_Not_GPR); in getEncodedGPR()
328 return GPRRegs[RegNum]; in getEncodedGPR()
331 static ByteRegister getEncodedByteReg(RegNumT RegNum) { in getEncodedByteReg()
340 RegNum.assertIsValid(); in getEncodedByteReg()
341 assert(ByteRegs[RegNum] != ByteRegister::Encoded_Not_ByteReg); in getEncodedByteReg()
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DIceTargetLoweringX8632Traits.h279 static const char *getRegName(RegNumT RegNum) { in getRegName()
288 RegNum.assertIsValid(); in getRegName()
289 return RegNames[RegNum]; in getRegName()
292 static GPRRegister getEncodedGPR(RegNumT RegNum) { in getEncodedGPR()
301 RegNum.assertIsValid(); in getEncodedGPR()
302 assert(GPRRegs[RegNum] != GPRRegister::Encoded_Not_GPR); in getEncodedGPR()
303 return GPRRegs[RegNum]; in getEncodedGPR()
306 static ByteRegister getEncodedByteReg(RegNumT RegNum) { in getEncodedByteReg()
315 RegNum.assertIsValid(); in getEncodedByteReg()
316 assert(ByteRegs[RegNum] != ByteRegister::Encoded_Not_ByteReg); in getEncodedByteReg()
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DIceRegAlloc.cpp434 const RegNumT RegNum = *RegNumBVIter(Iter.RegMask).begin(); in addSpillFill() local
435 Iter.Cur->setRegNumTmp(RegNum); in addSpillFill()
436 Variable *Preg = Target->getPhysicalRegister(RegNum, Iter.Cur->getType()); in addSpillFill()
621 const auto RegNum = Cur->getRegNum(); in allocatePrecoloredRegister() local
623 assert(Cur->getRegNumTmp() == RegNum); in allocatePrecoloredRegister()
626 const auto &Aliases = *RegAliases[RegNum]; in allocatePrecoloredRegister()
648 const RegNumT RegNum = in allocateFreeRegister() local
650 Iter.Cur->setRegNumTmp(RegNum); in allocateFreeRegister()
655 const auto &Aliases = *RegAliases[RegNum]; in allocateFreeRegister()
741 const auto RegNum = Item->getRegNumTmp(); in handleNoFreeRegisters() local
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DIceTargetLoweringX8664.cpp324 const auto RegNum = Var->getRegNum(); in isAssignedToRspOrRbp() local
325 if ((RegNum == Traits::RegisterSet::Reg_rsp) || in isAssignedToRspOrRbp()
326 (RegNum == Traits::RegisterSet::Reg_rbp)) { in isAssignedToRspOrRbp()
439 RegNumT RegNum, RegNum32; in _sandbox_mem_reference() local
442 RegNum = Traits::getGprForType(IceType_i64, T->getRegNum()); in _sandbox_mem_reference()
443 RegNum32 = Traits::getGprForType(IceType_i32, RegNum); in _sandbox_mem_reference()
446 assert(RegNum != Traits::RegisterSet::Reg_rsp); in _sandbox_mem_reference()
447 assert(RegNum != Traits::RegisterSet::Reg_rbp); in _sandbox_mem_reference()
459 Variable *T64 = makeReg(IceType_i64, RegNum); in _sandbox_mem_reference()
487 T = makeReg(IceType_i64, RegNum); in _sandbox_mem_reference()
DIceTargetLoweringMIPS32.h67 Variable *getPhysicalRegister(RegNumT RegNum,
69 const char *getRegName(RegNumT RegNum, Type Ty) const override;
666 RegNumT RegNum = RegNumT());
668 Variable *legalizeToVar(Operand *From, RegNumT RegNum = RegNumT());
670 Variable *legalizeToReg(Operand *From, RegNumT RegNum = RegNumT());
672 Variable *makeReg(Type Ty, RegNumT RegNum = RegNumT());
680 Variable *I32Reg(RegNumT RegNum = RegNumT()) {
681 return makeReg(IceType_i32, RegNum);
684 Variable *F32Reg(RegNumT RegNum = RegNumT()) {
685 return makeReg(IceType_f32, RegNum);
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DIceTargetLoweringX86BaseImpl.h915 Variable *TargetX86Base<TraitsType>::getPhysicalRegister(RegNumT RegNum,
921 assert(unsigned(RegNum) < PhysicalRegisters[Ty].size());
922 Variable *Reg = PhysicalRegisters[Ty][RegNum];
925 Reg->setRegNum(RegNum);
926 PhysicalRegisters[Ty][RegNum] = Reg;
934 assert(Traits::getGprForType(Ty, RegNum) == RegNum);
939 const char *TargetX86Base<TraitsType>::getRegName(RegNumT RegNum,
941 return Traits::getRegName(Traits::getGprForType(Ty, RegNum));
1092 for (RegNumT RegNum : RegNumBVIter(Pushed)) {
1093 assert(RegNum == Traits::getBaseReg(RegNum));
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DIceTargetLoweringX86Base.h108 Variable *getPhysicalRegister(RegNumT RegNum,
110 const char *getRegName(RegNumT RegNum, Type Ty) const override;
242 Operand *legalizeUndef(Operand *From, RegNumT RegNum = RegNumT());
416 RegNumT RegNum = RegNumT());
417 Variable *legalizeToReg(Operand *From, RegNumT RegNum = RegNumT());
426 Variable *makeReg(Type Ty, RegNumT RegNum = RegNumT());
441 Variable *copyToReg8(Operand *Src, RegNumT RegNum = RegNumT());
442 Variable *copyToReg(Operand *Src, RegNumT RegNum = RegNumT());
446 Variable *makeZeroedRegister(Type Ty, RegNumT RegNum = RegNumT());
450 Variable *makeVectorOfZeros(Type Ty, RegNumT RegNum = RegNumT());
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DIceTargetLoweringMIPS32.cpp238 RegNumT RegNum; in getCallStackArgumentsSizeBytes() local
239 if (CC.argInReg(Ty, i, &RegNum)) { in getCallStackArgumentsSizeBytes()
1048 const char *RegMIPS32::getRegName(RegNumT RegNum) { in getRegName() argument
1049 RegNum.assertIsValid(); in getRegName()
1050 return RegNames[RegNum]; in getRegName()
1053 const char *TargetMIPS32::getRegName(RegNumT RegNum, Type Ty) const { in getRegName() argument
1055 return RegMIPS32::getRegName(RegNum); in getRegName()
1058 Variable *TargetMIPS32::getPhysicalRegister(RegNumT RegNum, Type Ty) { in getPhysicalRegister() argument
1063 RegNum.assertIsValid(); in getPhysicalRegister()
1064 Variable *Reg = PhysicalRegisters[Ty][RegNum]; in getPhysicalRegister()
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DIceTargetLoweringARM32.cpp341 const auto RegNum = RegNumT::fromInt(i); in staticInit() local
343 GPRArgInitializer[Entry.CCArg - 1] = RegNum; in staticInit()
345 I64ArgInitializer[Entry.CCArg - 1] = RegNum; in staticInit()
347 FP32ArgInitializer[Entry.CCArg - 1] = RegNum; in staticInit()
349 FP64ArgInitializer[Entry.CCArg - 1] = RegNum; in staticInit()
351 Vec128ArgInitializer[Entry.CCArg - 1] = RegNum; in staticInit()
376 [](RegNumT RegNum) -> std::string { in staticInit() argument
379 std::string Name = RegARM32::getRegName(RegNum); in staticInit()
1187 const char *TargetARM32::getRegName(RegNumT RegNum, Type Ty) const { in getRegName() argument
1189 return RegARM32::getRegName(RegNum); in getRegName()
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DIceInstX8632.cpp105 const auto RegNum = Var->getRegNum(); in getRematerializableOffset() local
106 if (RegNum == Target->getFrameReg()) { in getRematerializableOffset()
108 } else if (RegNum != Target->getStackReg()) { in getRematerializableOffset()
DIceInstX8664.cpp95 const auto RegNum = Var->getRegNum(); in getRematerializableOffset() local
96 if (RegNum == Target->getFrameReg()) { in getRematerializableOffset()
98 } else if (RegNum != Target->getStackReg()) { in getRematerializableOffset()
/external/llvm/lib/MC/
DMCRegisterInfo.cpp61 int MCRegisterInfo::getDwarfRegNum(unsigned RegNum, bool isEH) const { in getDwarfRegNum() argument
65 DwarfLLVMRegPair Key = { RegNum, 0 }; in getDwarfRegNum()
67 if (I == M+Size || I->FromReg != RegNum) in getDwarfRegNum()
72 int MCRegisterInfo::getLLVMRegNum(unsigned RegNum, bool isEH) const { in getLLVMRegNum() argument
76 DwarfLLVMRegPair Key = { RegNum, 0 }; in getLLVMRegNum()
78 assert(I != M+Size && I->FromReg == RegNum && "Invalid RegNum"); in getLLVMRegNum()
82 int MCRegisterInfo::getSEHRegNum(unsigned RegNum) const { in getSEHRegNum()
83 const DenseMap<unsigned, int>::const_iterator I = L2SEHRegs.find(RegNum); in getSEHRegNum()
84 if (I == L2SEHRegs.end()) return (int)RegNum; in getSEHRegNum()
88 int MCRegisterInfo::getCodeViewRegNum(unsigned RegNum) const { in getCodeViewRegNum()
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/external/swiftshader/third_party/LLVM/include/llvm/MC/
DMCRegisterInfo.h263 int getDwarfRegNum(unsigned RegNum, bool isEH) const { in getDwarfRegNum() argument
265 const DenseMap<unsigned, int>::const_iterator I = M.find(RegNum); in getDwarfRegNum()
272 int getLLVMRegNum(unsigned RegNum, bool isEH) const { in getLLVMRegNum() argument
274 const DenseMap<unsigned, unsigned>::const_iterator I = M.find(RegNum); in getLLVMRegNum()
284 int getSEHRegNum(unsigned RegNum) const { in getSEHRegNum() argument
285 const DenseMap<unsigned, int>::const_iterator I = L2SEHRegs.find(RegNum); in getSEHRegNum()
286 if (I == L2SEHRegs.end()) return (int)RegNum; in getSEHRegNum()
/external/llvm/lib/Target/Hexagon/AsmParser/
DHexagonAsmParser.cpp184 unsigned RegNum; member
229 return Reg.RegNum; in getReg()
584 static std::unique_ptr<HexagonOperand> CreateReg(unsigned RegNum, SMLoc S, in CreateReg()
587 Op->Reg.RegNum = RegNum; in CreateReg()
1996 unsigned int RegNum = RI->getEncodingValue(Rs.getReg()); in processInstruction() local
1997 if (RegNum & 1) { // Odd mapped to raw:hi, regpair is rodd:odd-1, like r3:2 in processInstruction()
2000 r + llvm::utostr(RegNum) + Colon + llvm::utostr(RegNum - 1); in processInstruction()
2006 r + llvm::utostr(RegNum + 1) + Colon + llvm::utostr(RegNum); in processInstruction()
2015 unsigned int RegNum = RI->getEncodingValue(Rs.getReg()); in processInstruction() local
2016 if (RegNum & 1) { // Odd mapped to raw:hi in processInstruction()
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/external/swiftshader/third_party/LLVM/lib/Target/Mips/
DMipsAsmPrinter.cpp141 unsigned RegNum = MipsRegisterInfo::getRegisterNumbering(Reg); in printSavedRegsBitmask() local
143 FPUBitmask |= (3 << RegNum); in printSavedRegsBitmask()
149 FPUBitmask |= (1 << RegNum); in printSavedRegsBitmask()
156 unsigned RegNum = MipsRegisterInfo::getRegisterNumbering(Reg); in printSavedRegsBitmask() local
157 CPUBitmask |= (1 << RegNum); in printSavedRegsBitmask()
/external/llvm/lib/Target/Lanai/AsmParser/
DLanaiAsmParser.cpp51 bool ParseRegister(unsigned &RegNum, SMLoc &StartLoc, SMLoc &EndLoc) override;
106 unsigned RegNum; member
141 return Reg.RegNum; in getReg()
576 static std::unique_ptr<LanaiOperand> createReg(unsigned RegNum, SMLoc Start, in createReg()
579 Op->Reg.RegNum = RegNum; in createReg()
675 unsigned RegNum; in parseRegister() local
680 RegNum = MatchRegisterName(Lexer.getTok().getIdentifier()); in parseRegister()
681 if (RegNum == 0) in parseRegister()
684 return LanaiOperand::createReg(RegNum, Start, End); in parseRegister()
689 bool LanaiAsmParser::ParseRegister(unsigned &RegNum, SMLoc &StartLoc, in ParseRegister() argument
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/external/swiftshader/third_party/LLVM/lib/Target/MBlaze/AsmParser/
DMBlazeAsmParser.cpp92 unsigned RegNum; member
143 return Reg.RegNum; in getReg()
230 static MBlazeOperand *CreateReg(unsigned RegNum, SMLoc S, SMLoc E) { in CreateReg()
232 Op->Reg.RegNum = RegNum; in CreateReg()
/external/llvm/lib/Target/AArch64/AsmParser/
DAArch64AsmParser.cpp178 unsigned RegNum; member
183 unsigned RegNum; member
376 return Reg.RegNum; in getReg()
381 return VectorList.RegNum; in getVectorListStart()
911 Reg.RegNum); in isVectorRegLo()
915 AArch64MCRegisterClasses[AArch64::GPR64RegClassID].contains(Reg.RegNum); in isGPR32as64()
920 Reg.RegNum); in isWSeqPair()
925 Reg.RegNum); in isXSeqPair()
930 AArch64MCRegisterClasses[AArch64::GPR64spRegClassID].contains(Reg.RegNum); in isGPR64sp0()
1626 CreateReg(unsigned RegNum, bool isVector, SMLoc S, SMLoc E, MCContext &Ctx) { in CreateReg() argument
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/external/llvm/include/llvm/MC/
DMCRegisterInfo.h395 int getDwarfRegNum(unsigned RegNum, bool isEH) const;
398 int getLLVMRegNum(unsigned RegNum, bool isEH) const;
402 int getSEHRegNum(unsigned RegNum) const;
406 int getCodeViewRegNum(unsigned RegNum) const;
/external/llvm/test/CodeGen/X86/
Dstackmap-large-constants.ll40 ; Dwarf RegNum
70 ; Dwarf RegNum
/external/llvm/lib/CodeGen/
DStackMaps.cpp79 int RegNum = TRI->getDwarfRegNum(Reg, false); in getDwarfRegNum() local
80 for (MCSuperRegIterator SR(Reg, TRI); SR.isValid() && RegNum < 0; ++SR) in getDwarfRegNum()
81 RegNum = TRI->getDwarfRegNum(*SR, false); in getDwarfRegNum()
83 assert(RegNum >= 0 && "Invalid Dwarf register number."); in getDwarfRegNum()
84 return (unsigned)RegNum; in getDwarfRegNum()
/external/llvm/lib/Target/Sparc/AsmParser/
DSparcAsmParser.cpp202 unsigned RegNum; member
256 return Reg.RegNum; in getReg()
350 static std::unique_ptr<SparcOperand> CreateReg(unsigned RegNum, unsigned Kind, in CreateReg() argument
353 Op->Reg.RegNum = RegNum; in CreateReg()
383 Op.Reg.RegNum = IntPairRegs[regIdx / 2]; in MorphToIntPairReg()
394 Op.Reg.RegNum = DoubleRegs[regIdx / 2]; in MorphToDoubleReg()
417 Op.Reg.RegNum = Reg; in MorphToQuadReg()
430 Op.Reg.RegNum = CoprocPairRegs[regIdx / 2]; in MorphToCoprocPairReg()
/external/llvm/lib/Target/AMDGPU/AsmParser/
DAMDGPUAsmParser.cpp586 …terToList(unsigned& Reg, unsigned& RegWidth, RegisterKind RegKind, unsigned Reg1, unsigned RegNum);
587 …bool ParseAMDGPURegister(RegisterKind& RegKind, unsigned& Reg, unsigned& RegNum, unsigned& RegWidt…
804 …sterToList(unsigned& Reg, unsigned& RegWidth, RegisterKind RegKind, unsigned Reg1, unsigned RegNum) in AddNextRegisterToList() argument
825 bool AMDGPUAsmParser::ParseAMDGPURegister(RegisterKind& RegKind, unsigned& Reg, unsigned& RegNum, u… in ParseAMDGPURegister() argument
849 if (RegName.substr(RegNumIndex).getAsInteger(10, RegNum)) in ParseAMDGPURegister()
879 RegNum = (unsigned) RegLo; in ParseAMDGPURegister()
886 if (!ParseAMDGPURegister(RegKind, Reg, RegNum, RegWidth)) in ParseAMDGPURegister()
917 RegNum = 0; in ParseAMDGPURegister()
929 if (RegNum % Size != 0) in ParseAMDGPURegister()
931 RegNum = RegNum / Size; in ParseAMDGPURegister()
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