Home
last modified time | relevance | path

Searched refs:RegSize (Results 1 – 19 of 19) sorted by relevance

/external/swiftshader/third_party/LLVM/include/llvm/MC/
DMCRegisterInfo.h32 const unsigned RegSize, Alignment; // Size & Alignment of register in bytes variable
43 : ID(id), Name(name), RegSize(RS), Alignment(Al), CopyCost(CC), in MCRegisterClass()
91 unsigned getSize() const { return RegSize; } in getSize()
/external/llvm/lib/CodeGen/GlobalISel/
DRegisterBankInfo.cpp222 unsigned RegSize = 0; in getInstrMappingImpl() local
272 RegSize = getSizeInBits(Reg, MRI, TRI); in getInstrMappingImpl()
273 Mapping.setOperandMapping(OpIdx, RegSize, *CurRegBank); in getInstrMappingImpl()
300 Mapping.setOperandMapping(OpIdx, RegSize, *RegBank); in getInstrMappingImpl()
372 unsigned RegSize = MRI.getSize(Reg); in getSizeInBits() local
375 if (RegSize) in getSizeInBits()
376 return RegSize; in getSizeInBits()
/external/llvm/lib/CodeGen/AsmPrinter/
DDwarfExpression.cpp133 unsigned RegSize = TRI.getMinimalPhysRegClass(MachineReg)->getSize() * 8; in AddMachineRegPiece() local
136 SmallBitVector Coverage(RegSize, false); in AddMachineRegPiece()
145 SmallBitVector Intersection(RegSize, false); in AddMachineRegPiece()
/external/llvm/lib/Target/Mips/
DMipsSEFrameLowering.cpp60 void expandLoadACC(MachineBasicBlock &MBB, Iter I, unsigned RegSize);
62 unsigned MFLoOpc, unsigned RegSize);
179 unsigned RegSize) { in expandLoadACC() argument
187 const TargetRegisterClass *RC = RegInfo.intRegClass(RegSize); in expandLoadACC()
198 TII.loadRegFromStack(MBB, I, VR1, FI, RC, &RegInfo, RegSize); in expandLoadACC()
204 unsigned RegSize) { in expandStoreACC() argument
212 const TargetRegisterClass *RC = RegInfo.intRegClass(RegSize); in expandStoreACC()
222 TII.storeRegToStack(MBB, I, VR1, true, FI, RC, &RegInfo, RegSize); in expandStoreACC()
/external/llvm/lib/Target/AArch64/MCTargetDesc/
DAArch64AddressingModes.h213 static inline bool processLogicalImmediate(uint64_t Imm, unsigned RegSize, in processLogicalImmediate() argument
216 (RegSize != 64 && (Imm >> RegSize != 0 || Imm == ~0U))) in processLogicalImmediate()
220 unsigned Size = RegSize; in processLogicalImmediate()
/external/capstone/
DMCRegisterInfo.h39 uint16_t RegSize, Alignment; // Size & Alignment of register in bytes member
/external/swiftshader/third_party/LLVM/lib/Target/Mips/
DMipsFrameLowering.cpp154 unsigned RegSize = STI.isGP32bit() ? 4 : 8; in emitPrologue() local
157 (MFI->getObjectOffset(MipsFI->getGPFI()) + RegSize) : in emitPrologue()
/external/llvm/include/llvm/MC/
DMCRegisterInfo.h41 const uint16_t RegSize, Alignment; // Size & Alignment of register in bytes variable
82 unsigned getSize() const { return RegSize; } in getSize()
/external/llvm/lib/Target/SystemZ/
DSystemZInstrInfo.cpp740 LogicOp() : RegSize(0), ImmLSB(0), ImmSize(0) {} in LogicOp()
742 : RegSize(regSize), ImmLSB(immLSB), ImmSize(immSize) {} in LogicOp()
744 explicit operator bool() const { return RegSize; } in operator bool()
746 unsigned RegSize, ImmLSB, ImmSize; member
842 Imm |= allOnes(And.RegSize) & ~(allOnes(And.ImmSize) << And.ImmLSB); in convertToThreeAddress()
844 if (isRxSBGMask(Imm, And.RegSize, Start, End)) { in convertToThreeAddress()
846 if (And.RegSize == 64) { in convertToThreeAddress()
/external/llvm/lib/Target/AArch64/
DAArch64FastISel.cpp1616 unsigned RegSize; in emitLogicalOp_ri() local
1627 RegSize = 32; in emitLogicalOp_ri()
1633 RegSize = 64; in emitLogicalOp_ri()
1637 if (!AArch64_AM::isLogicalImmediate(Imm, RegSize)) in emitLogicalOp_ri()
1642 AArch64_AM::encodeLogicalImmediate(Imm, RegSize)); in emitLogicalOp_ri()
3946 unsigned RegSize = Is64Bit ? 64 : 32; in emitLSL_ri() local
3993 unsigned ImmR = RegSize - Shift; in emitLSL_ri()
4053 unsigned RegSize = Is64Bit ? 64 : 32; in emitLSR_ri() local
4101 return materializeInt(ConstantInt::get(*Context, APInt(RegSize, 0)), RetVT); in emitLSR_ri()
4174 unsigned RegSize = Is64Bit ? 64 : 32; in emitASR_ri() local
[all …]
/external/llvm/lib/Target/ARM/
DARMFrameLowering.cpp146 int RegSize; in sizeOfSPAdjustment() local
149 RegSize = 8; in sizeOfSPAdjustment()
153 RegSize = 4; in sizeOfSPAdjustment()
166 count += RegSize; in sizeOfSPAdjustment()
/external/clang/include/clang/Basic/
DTargetInfo.h692 unsigned RegSize, in validateGlobalRegisterVariable() argument
/external/llvm/lib/Target/Sparc/
DSparcISelLowering.cpp3184 unsigned RegSize = PVT.getStoreSize(); in emitEHSjLjLongJmp() local
3204 .addImm(RegSize); in emitEHSjLjLongJmp()
3211 .addImm(2 * RegSize); in emitEHSjLjLongJmp()
3217 .addImm(3 * RegSize); in emitEHSjLjLongJmp()
3237 unsigned RegSize = PVT.getStoreSize(); in emitEHSjLjSetJmp() local
3308 .addImm(RegSize) in emitEHSjLjSetJmp()
3315 .addImm(2 * RegSize) in emitEHSjLjSetJmp()
3321 .addImm(3 * RegSize) in emitEHSjLjSetJmp()
/external/clang/lib/CodeGen/
DTargetInfo.cpp3764 CharUnits RegSize = CharUnits::fromQuantity((isInt || IsSoftFloatABI) ? 4 : 8); in EmitVAArg() local
3766 Builder.CreateMul(NumRegs, Builder.getInt8(RegSize.getQuantity())); in EmitVAArg()
3769 RegAddr.getAlignment().alignmentOfArrayElement(RegSize)); in EmitVAArg()
4729 int RegSize = IsIndirect ? 8 : TyInfo.first.getQuantity(); in EmitAAPCSVAArg() local
4738 RegSize = llvm::alignTo(RegSize, 8); in EmitAAPCSVAArg()
4747 RegSize = 16 * NumRegs; in EmitAAPCSVAArg()
4788 reg_offs, llvm::ConstantInt::get(CGF.Int32Ty, RegSize), "new_reg_offs"); in EmitAAPCSVAArg()
/external/swiftshader/third_party/LLVM/lib/CodeGen/SelectionDAG/
DSelectionDAGBuilder.cpp684 unsigned RegSize = RegisterVT.getSizeInBits(); in getCopyFromRegs() local
692 if (NumSignBits == RegSize) in getCopyFromRegs()
694 else if (NumZeroBits >= RegSize-1) in getCopyFromRegs()
696 else if (NumSignBits > RegSize-8) in getCopyFromRegs()
698 else if (NumZeroBits >= RegSize-8) in getCopyFromRegs()
700 else if (NumSignBits > RegSize-16) in getCopyFromRegs()
702 else if (NumZeroBits >= RegSize-16) in getCopyFromRegs()
704 else if (NumSignBits > RegSize-32) in getCopyFromRegs()
706 else if (NumZeroBits >= RegSize-32) in getCopyFromRegs()
/external/llvm/lib/CodeGen/SelectionDAG/
DSelectionDAGBuilder.cpp683 unsigned RegSize = RegisterVT.getSizeInBits(); in getCopyFromRegs() local
687 if (NumZeroBits == RegSize) { in getCopyFromRegs()
699 if (NumSignBits == RegSize) { in getCopyFromRegs()
702 } else if (NumZeroBits >= RegSize - 1) { in getCopyFromRegs()
705 } else if (NumSignBits > RegSize - 8) { in getCopyFromRegs()
708 } else if (NumZeroBits >= RegSize - 8) { in getCopyFromRegs()
711 } else if (NumSignBits > RegSize - 16) { in getCopyFromRegs()
714 } else if (NumZeroBits >= RegSize - 16) { in getCopyFromRegs()
717 } else if (NumSignBits > RegSize - 32) { in getCopyFromRegs()
720 } else if (NumZeroBits >= RegSize - 32) { in getCopyFromRegs()
/external/clang/lib/Basic/
DTargets.cpp2641 unsigned RegSize, in validateGlobalRegisterVariable() argument
2647 HasSizeMismatch = RegSize != 32; in validateGlobalRegisterVariable()
4386 unsigned RegSize, in validateGlobalRegisterVariable() argument
4392 HasSizeMismatch = RegSize != 64; in validateGlobalRegisterVariable()
4397 return X86TargetInfo::validateGlobalRegisterVariable(RegName, RegSize, in validateGlobalRegisterVariable()
/external/llvm/lib/Target/X86/
DX86ISelLowering.cpp21812 const unsigned RegSize = in ReplaceNodeResults() local
21814 assert((!Subtarget.hasAVX512() || RegSize < 512) && in ReplaceNodeResults()
21816 assert((!Subtarget.hasAVX2() || RegSize < 256) && in ReplaceNodeResults()
21821 RegSize / ElemVT.getSizeInBits()); in ReplaceNodeResults()
21822 assert(RegSize % InVT.getSizeInBits() == 0); in ReplaceNodeResults()
21823 unsigned NumConcat = RegSize / InVT.getSizeInBits(); in ReplaceNodeResults()
27504 unsigned RegSize = 128; in reduceVMULWidth() local
27505 MVT OpsVT = MVT::getVectorVT(MVT::i16, RegSize / 16); in reduceVMULWidth()
27556 SmallVector<SDValue, 16> Ops(RegSize / ReducedVT.getSizeInBits(), in reduceVMULWidth()
27569 MVT ResVT = MVT::getVectorVT(MVT::i32, RegSize / 32); in reduceVMULWidth()
[all …]
DX86InstrInfo.cpp6170 unsigned RegSize = in isNonFoldablePartialRegisterLoad() local
6173 if ((Opc == X86::MOVSSrm || Opc == X86::VMOVSSrm) && RegSize > 4) { in isNonFoldablePartialRegisterLoad()
6194 if ((Opc == X86::MOVSDrm || Opc == X86::VMOVSDrm) && RegSize > 8) { in isNonFoldablePartialRegisterLoad()