| /external/llvm/lib/Target/AMDGPU/ |
| D | AMDGPUAsmPrinter.cpp | 117 const AMDGPUSubtarget &STM = MF->getSubtarget<AMDGPUSubtarget>(); in EmitFunctionBodyStart() local
119 if (STM.isAmdHsaOS()) { in EmitFunctionBodyStart()
127 const AMDGPUSubtarget &STM = MF->getSubtarget<AMDGPUSubtarget>(); in EmitFunctionEntryLabel() local
128 if (MFI->isKernel() && STM.isAmdHsaOS()) { in EmitFunctionEntryLabel()
159 const AMDGPUSubtarget &STM = MF.getSubtarget<AMDGPUSubtarget>(); in runOnMachineFunction() local
161 if (STM.getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS) { in runOnMachineFunction()
163 if (!STM.isAmdHsaOS()) { in runOnMachineFunction()
181 if (STM.getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS) { in runOnMachineFunction()
233 if (STM.dumpCode()) { in runOnMachineFunction()
253 const R600Subtarget &STM = MF.getSubtarget<R600Subtarget>(); in EmitProgramInfoR600() local
[all …]
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| D | SILoadStoreOptimizer.cpp | 414 const SISubtarget &STM = MF.getSubtarget<SISubtarget>(); in runOnMachineFunction() local
415 if (!STM.loadStoreOptEnabled()) in runOnMachineFunction()
418 TII = STM.getInstrInfo(); in runOnMachineFunction()
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| /external/nos/test/system-test-harness/src/test-data/NIST-CAVP/ |
| D | README | 4 AES-GCM: http://csrc.nist.gov/groups/STM/cavp/documents/mac/gcmtestvectors.zip
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| /external/swiftshader/third_party/LLVM/test/MC/Disassembler/ARM/ |
| D | invalid-t2PUSH-thumb.txt | 3 # SP and PC are not allowed in the register list on STM instructions in Thumb2.
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| D | thumb1.txt | 377 # STM
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| /external/llvm/test/CodeGen/ARM/ |
| D | load-store-flags.ll | 26 ; past it to form the STM.
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| /external/swiftshader/third_party/LLVM/utils/TableGen/ |
| D | DAGISelMatcherEmitter.cpp | 725 } else if (const SwitchTypeMatcher *STM = dyn_cast<SwitchTypeMatcher>(M)) { in BuildHistogram() local
726 for (unsigned i = 0, e = STM->getNumCases(); i != e; ++i) in BuildHistogram()
727 BuildHistogram(STM->getCaseMatcher(i), OpcodeFreq); in BuildHistogram()
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| /external/llvm/utils/TableGen/ |
| D | DAGISelMatcherEmitter.cpp | 761 } else if (const SwitchTypeMatcher *STM = dyn_cast<SwitchTypeMatcher>(M)) { in BuildHistogram() local
762 for (unsigned i = 0, e = STM->getNumCases(); i != e; ++i) in BuildHistogram()
763 BuildHistogram(STM->getCaseMatcher(i), OpcodeFreq); in BuildHistogram()
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| /external/swiftshader/third_party/LLVM/lib/Target/ |
| D | TargetData.cpp | 356 StructLayoutMap *STM = static_cast<StructLayoutMap*>(LayoutMap); in getStructLayout() local
357 StructLayout *&SL = (*STM)[Ty]; in getStructLayout()
|
| /external/llvm/lib/IR/ |
| D | DataLayout.cpp | 560 StructLayoutMap *STM = static_cast<StructLayoutMap*>(LayoutMap); in getStructLayout() local
561 StructLayout *&SL = (*STM)[Ty]; in getStructLayout()
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| /external/llvm/test/MC/Disassembler/ARM/ |
| D | invalid-thumbv7.txt | 134 # SP and PC are not allowed in the register list on STM instructions in Thumb2.
360 # 32-bit Thumb STM instructions cannot have a writeback register which appears
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| D | thumb1.txt | 386 # STM
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| /external/swiftshader/third_party/LLVM/test/MC/ARM/ |
| D | thumb-diagnostics.s | 71 @ Invalid writeback and register lists for STM
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| D | diagnostics.s | 216 @ Out of order STM registers
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| D | basic-thumb-instructions.s | 467 @ STM
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| /external/llvm/lib/Target/ARM/ |
| D | ARMScheduleSwift.td | 519 (instregex "STM(IB|IA|DB|DA)$", "(t2|sys|t)STM(IB|IA|DB|DA)$")>;
521 (instregex "STM(IB|IA|DB|DA)_UPD", "(t2|sys|t)STM(IB|IA|DB|DA)_UPD",
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| D | ARMBaseInstrInfo.cpp | 1238 MachineInstrBuilder LDM, STM; in expandMEMCPY() local
1249 STM = BuildMI(*BB, MI, dl, TII->get(isThumb2 ? ARM::t2STMIA_UPD in expandMEMCPY()
1254 STM = BuildMI(*BB, MI, dl, TII->get(isThumb2 ? ARM::t2STMIA : ARM::STMIA)); in expandMEMCPY()
1258 AddDefaultPred(STM.addOperand(MI->getOperand(2))); in expandMEMCPY()
1274 STM.addReg(Reg, RegState::Kill); in expandMEMCPY()
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| /external/boringssl/src/crypto/fipsmodule/ |
| D | FIPS.md | 5 …. Please consult with an [accredited CMVP lab](http://csrc.nist.gov/groups/STM/testing_labs/) on t…
11 1. 2017-06-15: certificate [#2964](http://csrc.nist.gov/groups/STM/cmvp/documents/140-1/1401val2017…
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| /external/llvm/test/CodeGen/SystemZ/ |
| D | frame-05.ll | 10 ; itself would allow STM and LM to be used instead of STMG and LMG.
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| /external/llvm/test/MC/ARM/ |
| D | diagnostics.s | 285 @ Out of order STM registers
488 @ CHECK-ERRORS: error: system STM cannot have writeback register
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| D | thumb-diagnostics.s | 119 @ Invalid writeback and register lists for STM
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| D | basic-thumb-instructions.s | 518 @ STM
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| /external/libunwind_llvm/src/ |
| D | UnwindRegistersSave.S | 474 @ . the pc (r15) cannot be in the list in an STM instruction
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| /external/boringssl/src/crypto/ecdh/ |
| D | ecdh_tests.txt | 2 # http://csrc.nist.gov/groups/STM/cavp/documents/components/ecccdhtestvectors.zip
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| /external/v8/src/s390/ |
| D | disasm-s390.cc | 637 case STM: in DecodeFourByte()
|