| /external/swiftshader/third_party/LLVM/test/CodeGen/Alpha/ |
| D | sub128.ll | 1 ;test for SUBC and SUBE expansion
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| /external/llvm/lib/Target/Mips/ |
| D | Mips16ISelDAGToDAG.cpp | 194 case ISD::SUBE: in trySelect()
200 (Opc == ISD::SUBC || Opc == ISD::SUBE)) && in trySelect()
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| D | MipsSEISelDAGToDAG.cpp | 246 (Opc == ISD::SUBC || Opc == ISD::SUBE)) && in selectAddESubE()
732 case ISD::SUBE: { in trySelect()
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| D | MipsSEISelLowering.cpp | 143 setTargetDAGCombine(ISD::SUBE); in MipsSETargetLowering()
1081 case ISD::SUBE: in PerformDAGCombine()
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| /external/llvm/lib/Target/Lanai/ |
| D | LanaiAluCode.h | 127 case ISD::SUBE: in isdToLanaiAluCode()
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| /external/swiftshader/third_party/LLVM/lib/Target/Mips/ |
| D | MipsISelDAGToDAG.cpp | 209 case ISD::SUBE: in Select()
214 (Opc == ISD::SUBC || Opc == ISD::SUBE)) && in Select()
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| D | MipsISelLowering.cpp | 218 setTargetDAGCombine(ISD::SUBE); in MipsTargetLowering()
646 case ISD::SUBE: in PerformDAGCombine()
|
| /external/swiftshader/third_party/LLVM/include/llvm/CodeGen/ |
| D | ISDOpcodes.h | 217 ADDE, SUBE, enumerator
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| /external/llvm/include/llvm/CodeGen/ |
| D | ISDOpcodes.h | 223 ADDE, SUBE, enumerator
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| /external/swiftshader/third_party/LLVM/lib/Target/Blackfin/ |
| D | BlackfinISelLowering.cpp | 99 setOperationAction(ISD::SUBE, MVT::i32, Custom); in BlackfinTargetLowering()
472 case ISD::SUBE: return LowerADDE(Op, DAG); in LowerOperation()
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| /external/swiftshader/third_party/LLVM/lib/Target/ARM/ |
| D | ARMISelLowering.h | 77 SUBE, // Sub using carry enumerator
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| D | ARMISelLowering.cpp | 569 setOperationAction(ISD::SUBE, MVT::i32, Custom); in ARMTargetLowering()
847 case ARMISD::SUBE: return "ARMISD::SUBE"; in getTargetNodeName()
4881 case ISD::SUBE: Opc = ARMISD::SUBE; ExtraOp = true; break; in LowerADDC_ADDE_SUBC_SUBE()
4985 case ISD::SUBE: return LowerADDC_ADDE_SUBC_SUBE(Op, DAG); in LowerOperation()
|
| /external/llvm/lib/Target/ARM/ |
| D | ARMISelLowering.h | 74 SUBE, // Sub using carry enumerator
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| D | ARMISelLowering.cpp | 747 setOperationAction(ISD::SUBE, MVT::i32, Custom); in ARMTargetLowering()
1149 case ARMISD::SUBE: return "ARMISD::SUBE"; in getTargetNodeName()
5021 SDValue Cmp = DAG.getNode(ARMISD::SUBE, DL, VTs, LHS, RHS, Carry); in LowerSETCCE()
6902 case ISD::SUBE: Opc = ARMISD::SUBE; ExtraOp = true; break; in LowerADDC_ADDE_SUBC_SUBE()
7209 case ISD::SUBE: return LowerADDC_ADDE_SUBC_SUBE(Op, DAG); in LowerOperation()
11640 case ARMISD::SUBE: in computeKnownBitsForTargetNode()
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| /external/llvm/lib/CodeGen/SelectionDAG/ |
| D | SelectionDAGDumper.cpp | 235 case ISD::SUBE: return "sube"; in getOperationName()
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| D | LegalizeIntegerTypes.cpp | 1391 case ISD::SUBE: ExpandIntRes_ADDSUBE(N, Lo, Hi); break; in ExpandIntegerResult()
1755 Hi = DAG.getNode(ISD::SUBE, dl, VTList, HiOps); in ExpandIntRes_ADDSUB()
1836 Hi = DAG.getNode(ISD::SUBE, dl, VTList, HiOps); in ExpandIntRes_ADDSUBC()
3003 SDValue LowCmp = DAG.getNode(ISD::SUBE, dl, VTList, LHSLo, RHSLo, Carry); in ExpandIntOp_SETCCE()
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| /external/llvm/lib/Target/BPF/ |
| D | BPFISelLowering.cpp | 93 setOperationAction(ISD::SUBE, MVT::i64, Expand); in BPFTargetLowering()
|
| /external/llvm/lib/Target/WebAssembly/ |
| D | WebAssemblyISelLowering.cpp | 100 ISD::SUBE}) { in WebAssemblyTargetLowering()
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| /external/llvm/lib/Target/Hexagon/ |
| D | HexagonISelLowering.cpp | 1838 setOperationAction(ISD::SUBE, MVT::i8, Expand); in HexagonTargetLowering()
1839 setOperationAction(ISD::SUBE, MVT::i16, Expand); in HexagonTargetLowering()
1840 setOperationAction(ISD::SUBE, MVT::i32, Expand); in HexagonTargetLowering()
1841 setOperationAction(ISD::SUBE, MVT::i64, Expand); in HexagonTargetLowering()
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| /external/llvm/lib/Target/Sparc/ |
| D | SparcISelLowering.cpp | 1616 setOperationAction(ISD::SUBE, MVT::i64, Custom); in SparcTargetLowering()
2931 case ISD::SUBC: hiOpc = ISD::SUBE; break; in LowerADDC_ADDE_SUBC_SUBE()
2932 case ISD::SUBE: hasChain = true; break; in LowerADDC_ADDE_SUBC_SUBE()
3080 case ISD::SUBE: return LowerADDC_ADDE_SUBC_SUBE(Op, DAG); in LowerOperation()
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| /external/swiftshader/third_party/LLVM/lib/CodeGen/SelectionDAG/ |
| D | LegalizeIntegerTypes.cpp | 1146 case ISD::SUBE: ExpandIntRes_ADDSUBE(N, Lo, Hi); break; in ExpandIntegerResult()
1531 Hi = DAG.getNode(ISD::SUBE, dl, VTList, HiOps, 3); in ExpandIntRes_ADDSUB()
1580 Hi = DAG.getNode(ISD::SUBE, dl, VTList, HiOps, 3); in ExpandIntRes_ADDSUBC()
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| /external/swiftshader/third_party/LLVM/lib/Target/Alpha/ |
| D | AlphaISelLowering.cpp | 105 setOperationAction(ISD::SUBE , MVT::i64, Expand); in AlphaTargetLowering()
|
| /external/swiftshader/third_party/LLVM/lib/Target/XCore/ |
| D | XCoreISelLowering.cpp | 92 setOperationAction(ISD::SUBE, MVT::i32, Expand); in XCoreTargetLowering()
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| /external/swiftshader/third_party/LLVM/include/llvm/Target/ |
| D | TargetSelectionDAG.td | 347 def sube : SDNode<"ISD::SUBE" , SDTIntBinOp,
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| /external/llvm/include/llvm/Target/ |
| D | TargetSelectionDAG.td | 397 def sube : SDNode<"ISD::SUBE" , SDTIntBinOp,
|