Searched refs:SWR (Results 1 – 21 of 21) sorted by relevance
| /external/mesa3d/src/gallium/docs/source/drivers/openswr/ |
| D | faq.rst | 26 SWR is a tile based immediate mode renderer with a sort-free threading
38 shader and fragment shaders, streamout, and fragment blending. SWR
72 of writing. Core SWR undergoes rigorous unit testing and we are quite
77 and SWR. Fixing these issues is one of our major future development
100 * Features - core SWR has a lot of functionality we have yet to
132 * You don't need a fire-breathing Xeon machine to work on SWR - we do
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| D | usage.rst | 37 SWR detected AVX2
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| /external/tcpdump/tests/ |
| D | pimv2_sm-v.out | 20 joined source #1: 1.1.1.1(SWR)
54 joined source #1: 1.1.1.1(SWR)
90 joined source #1: 1.1.1.1(SWR)
124 joined source #1: 1.1.1.1(SWR)
160 joined source #1: 1.1.1.1(SWR)
196 joined source #1: 1.1.1.1(SWR)
230 joined source #1: 1.1.1.1(SWR)
266 joined source #1: 1.1.1.1(SWR)
286 pruned source #1: 1.1.1.1(SWR)
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| /external/llvm/lib/Target/Mips/MCTargetDesc/ |
| D | MipsNaClELFStreamer.cpp | 233 case Mips::SWR: in isBasePlusOffsetMemoryAccess()
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| /external/mesa3d/src/gallium/drivers/swr/ |
| D | SConscript | 202 # main SWR lib
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| /external/v8/src/mips/ |
| D | constants-mips.h | 383 SWR = ((5U << 3) + 6) << kOpcodeShift, enumerator
917 OpcodeToBitNumber(SWL) | OpcodeToBitNumber(SW) | OpcodeToBitNumber(SWR) |
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| D | disasm-mips.cc | 1642 case SWR: in DecodeTypeImmediate()
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| D | assembler-mips.cc | 1945 GenInstrImmediate(SWR, rs.rm(), rd, rs.offset_); in swr()
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| D | simulator-mips.cc | 4507 case SWR: { in DecodeTypeImmediate()
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| /external/v8/src/mips64/ |
| D | constants-mips64.h | 362 SWR = ((5U << 3) + 6) << kOpcodeShift, enumerator
952 OpcodeToBitNumber(SWR) | OpcodeToBitNumber(SDR) |
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| D | disasm-mips64.cc | 1859 case SWR: in DecodeTypeImmediate()
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| D | assembler-mips64.cc | 2114 GenInstrImmediate(SWR, rs.rm(), rd, rs.offset_); in swr()
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| D | simulator-mips64.cc | 4754 case SWR: { in DecodeTypeImmediate()
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| /external/llvm/lib/Target/Mips/ |
| D | MipsISelLowering.h | 205 SWR, enumerator
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| D | MipsInstrInfo.td | 138 def MipsSWR : SDNode<"MipsISD::SWR", SDTStore,
1773 def SWR : StoreLeftRight<"swr", MipsSWR, GPR32Opnd, II_SWR>, LW_FM<0x2e>,
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| D | MipsISelLowering.cpp | 150 case MipsISD::SWR: return "MipsISD::SWR"; in getTargetNodeName()
2358 return createStoreLR(MipsISD::SWR, DAG, SD, SWL, IsLittle ? 0 : 3); in lowerUnalignedIntStore()
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| /external/swiftshader/third_party/LLVM/lib/Target/MBlaze/Disassembler/ |
| D | MBlazeDisassembler.cpp | 400 case 0x1: return MBlaze::SWR; in decodeSW()
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| /external/swiftshader/third_party/LLVM/lib/Target/MBlaze/ |
| D | MBlazeInstrInfo.td | 472 def SWR : StoreM<0x36, 0x200, "swr ">;
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| /external/v8/src/s390/ |
| D | constants-s390.h | 1573 V(swr, SWR, 0x2F) /* type = RR SUBTRACT UNNORMALIZED (long HFP) */ \
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| /external/capstone/arch/Mips/ |
| D | MipsGenAsmWriter.inc | 1603 12605435U, // SWR
3317 0U, // SWR
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| D | MipsGenDisassemblerTables.inc | 3597 /* 13194 */ MCD_OPC_Decode, 178, 12, 194, 1, // Opcode: SWR
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