| /external/vixl/src/aarch64/ |
| D | operands-aarch64.cc | 322 VIXL_ASSERT(reg.Is64Bits() || ((extend != SXTX) && (extend != UXTX))); in Operand()
342 (((extend_ == UXTX) || (extend_ == SXTX)) && (shift_amount_ == 0))); in IsPlainRegister()
407 VIXL_ASSERT((extend == UXTW) || (extend == SXTW) || (extend == SXTX)); in MemOperand()
410 VIXL_ASSERT(regoffset.Is64Bits() || (extend != SXTX)); in MemOperand()
468 VIXL_ASSERT((extend_ == UXTW) || (extend_ == SXTW) || (extend_ == SXTX)); in MemOperand()
469 VIXL_ASSERT((regoffset_.Is64Bits() || (extend_ != SXTX))); in MemOperand()
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| D | macro-assembler-aarch64.cc | 899 ((operand.GetExtend() != UXTX) && (operand.GetExtend() != SXTX))); in LogicalMacro()
1812 ((operand.GetExtend() != UXTX) && (operand.GetExtend() != SXTX))); in AddSubWithCarryMacro()
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| D | disasm-aarch64.cc | 165 const char *form = ((mode == UXTX) || (mode == SXTX)) ? "'Rds, 'Rns, 'Xm'Ext" in VisitAddSubExtended()
168 ((mode == UXTX) || (mode == SXTX)) ? "'Rns, 'Xm'Ext" : "'Rns, 'Wm'Ext"; in VisitAddSubExtended()
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| D | constants-aarch64.h | 293 SXTX = 7 enumerator
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| D | simulator-aarch64.cc | 416 case SXTX: in ExtendValue()
1287 VIXL_ASSERT((ext == UXTW) || (ext == UXTX) || (ext == SXTW) || (ext == SXTX)); in VisitLoadStoreRegisterOffset()
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| D | assembler-aarch64.cc | 4203 case SXTX: { in EmitExtendShift()
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| /external/llvm/lib/Target/AArch64/MCTargetDesc/ |
| D | AArch64AddressingModes.h | 48 SXTX, enumerator
67 case AArch64_AM::SXTX: return "sxtx"; in getShiftExtendName()
134 case 7: return AArch64_AM::SXTX; in getExtendType()
161 case AArch64_AM::SXTX: return 7; break; in getExtendEncoding()
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| /external/v8/src/arm64/ |
| D | assembler-arm64-inl.h | 352 DCHECK(reg.Is64Bits() || ((extend != SXTX) && (extend != UXTX)));
466 DCHECK((extend == UXTW) || (extend == SXTW) || (extend == SXTX));
469 DCHECK(regoffset.Is64Bits() || (extend != SXTX));
519 DCHECK((extend_ == UXTW) || (extend_ == SXTW) || (extend_ == SXTX));
520 DCHECK((regoffset_.Is64Bits() || (extend_ != SXTX)));
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| D | disasm-arm64.cc | 144 const char *form = ((mode == UXTX) || (mode == SXTX)) ? in VisitAddSubExtended()
146 const char *form_cmp = ((mode == UXTX) || (mode == SXTX)) ? in VisitAddSubExtended()
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| D | constants-arm64.h | 346 SXTX = 7 enumerator
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| D | simulator-arm64.cc | 996 case SXTX: in ExtendValue()
1615 DCHECK((ext == UXTW) || (ext == UXTX) || (ext == SXTW) || (ext == SXTX)); in VisitLoadStoreRegisterOffset()
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| D | macro-assembler-arm64.cc | 147 ((operand.extend() != UXTX) && (operand.extend() != SXTX))); in LogicalMacro()
549 ((operand.extend() != UXTX) && (operand.extend() != SXTX))); in AddSubWithCarryMacro()
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| D | assembler-arm64.cc | 2507 case SXTX: { in EmitExtendShift()
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| /external/vixl/test/aarch64/ |
| D | test-api-aarch64.cc | 294 VIXL_CHECK(Operand(x6, SXTX).IsPlainRegister()); in TEST()
306 VIXL_CHECK(!Operand(x6, SXTX, 2).IsPlainRegister()); in TEST()
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| D | test-disasm-aarch64.cc | 439 COMPARE(adds(x27, x28, Operand(x29, SXTX)), "adds x27, x28, x29, sxtx"); in TEST()
465 COMPARE(subs(x27, x28, Operand(x29, SXTX)), "subs x27, x28, x29, sxtx"); in TEST()
1064 COMPARE(ldr(w18, MemOperand(x19, x20, SXTX)), "ldr w18, [x19, x20, sxtx]"); in TEST()
1065 COMPARE(ldr(w21, MemOperand(x22, x23, SXTX, 2)), in TEST()
1074 COMPARE(ldr(x18, MemOperand(x19, x20, SXTX)), "ldr x18, [x19, x20, sxtx]"); in TEST()
1075 COMPARE(ldr(x21, MemOperand(x22, x23, SXTX, 3)), in TEST()
1085 COMPARE(str(w18, MemOperand(x19, x20, SXTX)), "str w18, [x19, x20, sxtx]"); in TEST()
1086 COMPARE(str(w21, MemOperand(x22, x23, SXTX, 2)), in TEST()
1095 COMPARE(str(x18, MemOperand(x19, x20, SXTX)), "str x18, [x19, x20, sxtx]"); in TEST()
1096 COMPARE(str(x21, MemOperand(x22, x23, SXTX, 3)), in TEST()
[all …]
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| D | test-assembler-aarch64.cc | 745 __ Orr(x13, x0, Operand(x1, SXTX, 3)); in TEST()
839 __ Orn(x13, x0, Operand(x1, SXTX, 3)); in TEST()
906 __ And(x13, x0, Operand(x1, SXTX, 3)); in TEST()
1044 __ Bic(x13, x0, Operand(x1, SXTX, 3)); in TEST()
1168 __ Eor(x13, x0, Operand(x1, SXTX, 3)); in TEST()
1235 __ Eon(x13, x0, Operand(x1, SXTX, 3)); in TEST()
7714 __ Prfm(op, MemOperand(x0, input, SXTX)); in TEST()
7715 __ Prfm(op, MemOperand(x0, input, SXTX, 3)); in TEST()
8821 __ Adcs(x10, x0, Operand(x1, SXTX, 1)); in TEST()
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| /external/llvm/lib/Target/AArch64/Utils/ |
| D | AArch64BaseInfo.h | 367 SXTX enumerator
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| /external/llvm/lib/Target/AArch64/AsmParser/ |
| D | AArch64AsmParser.cpp | 991 ET == AArch64_AM::UXTX || ET == AArch64_AM::SXTX || in isExtend()
1001 return ET != AArch64_AM::UXTX && ET != AArch64_AM::SXTX; in isExtend64()
1007 return (ET == AArch64_AM::UXTX || ET == AArch64_AM::SXTX || in isExtendLSL64()
1016 return (ET == AArch64_AM::LSL || ET == AArch64_AM::SXTX) && in isMemXExtend()
1577 bool IsSigned = ET == AArch64_AM::SXTW || ET == AArch64_AM::SXTX; in addMemExtendOperands()
1589 bool IsSigned = ET == AArch64_AM::SXTW || ET == AArch64_AM::SXTX; in addMemExtend8Operands()
2396 .Case("sxtx", AArch64_AM::SXTX) in tryParseOptionalShiftExtend()
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| /external/llvm/lib/Target/AArch64/ |
| D | AArch64ISelDAGToDAG.cpp | 596 assert(Ext != AArch64_AM::UXTX && Ext != AArch64_AM::SXTX); in SelectArithExtendedRegister()
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| D | AArch64FastISel.cpp | 1068 Addr.getExtendType() == AArch64_AM::SXTX; in addLoadStoreOperands()
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| D | AArch64InstrFormats.td | 1781 // UXTX and SXTX only.
1855 // UXTX and SXTX only.
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