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Searched refs:SchedRW (Results 1 – 23 of 23) sorted by relevance

/external/llvm/utils/TableGen/
DCodeGenSchedule.cpp403 const CodeGenSchedRW &SchedRW = getSchedRW(RWIdx, IsRead); in expandRWSequence() local
404 if (!SchedRW.IsSequence) { in expandRWSequence()
409 SchedRW.TheDef ? SchedRW.TheDef->getValueAsInt("Repeat") : 1; in expandRWSequence()
411 for (IdxIter I = SchedRW.Sequence.begin(), E = SchedRW.Sequence.end(); in expandRWSequence()
485 CodeGenSchedRW SchedRW(RWIdx, IsRead, Seq, genRWName(Seq, IsRead)); in findOrInsertRW() local
487 SchedReads.push_back(SchedRW); in findOrInsertRW()
489 SchedWrites.push_back(SchedRW); in findOrInsertRW()
968 const CodeGenSchedRW &SchedRW, unsigned TransIdx,
991 const CodeGenSchedRW &SchedRW = SchedModels.getSchedRW(I->RWIdx, I->IsRead); in mutuallyExclusive() local
992 assert(SchedRW.HasVariants && "PredCheck must refer to a SchedVariant"); in mutuallyExclusive()
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/external/llvm/lib/Target/X86/
DX86InstrSystem.td16 let SchedRW = [WriteSystem] in {
39 } // SchedRW
45 let SchedRW = [WriteSystem] in {
63 } // SchedRW
73 let SchedRW = [WriteSystem] in {
114 } // SchedRW
119 let SchedRW = [WriteSystem] in {
133 } // SchedRW
138 let SchedRW = [WriteSystem] in {
152 } // SchedRW
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DX86InstrFPStack.td243 let SchedRW = [WriteFAddLd] in {
248 let SchedRW = [WriteFMulLd] in {
251 let SchedRW = [WriteFDivLd] in {
267 let SchedRW = [WriteFAdd] in {
277 } // SchedRW
278 let SchedRW = [WriteFMul] in {
282 } // SchedRW
283 let SchedRW = [WriteFDiv] in {
290 } // SchedRW
309 let SchedRW = [WriteFSqrt] in {
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DX86InstrInfo.td1059 let hasSideEffects = 0, SchedRW = [WriteZero] in {
1072 let SchedRW = [WriteALU] in {
1082 } // SchedRW
1093 let mayLoad = 1, SchedRW = [WriteLoad] in {
1106 } // mayLoad, SchedRW
1108 let mayStore = 1, SchedRW = [WriteStore] in {
1129 } // mayStore, SchedRW
1131 let mayLoad = 1, mayStore = 1, SchedRW = [WriteRMW] in {
1136 } // mayLoad, mayStore, SchedRW
1141 SchedRW = [WriteRMW], Defs = [ESP] in {
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DX86InstrArithmetic.td17 let SchedRW = [WriteLEA] in {
39 } // SchedRW
154 let isCommutable = 1, SchedRW = [WriteIMul] in {
173 } // isCommutable, SchedRW
176 let SchedRW = [WriteIMulLd, ReadAfterLd] in {
198 } // SchedRW
205 let SchedRW = [WriteIMul] in {
243 } // SchedRW
246 let SchedRW = [WriteIMulLd] in {
288 } // SchedRW
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DX86InstrShiftRotate.td18 let Constraints = "$src1 = $dst", SchedRW = [WriteShift] in {
66 } // Constraints = "$src = $dst", SchedRW
69 let SchedRW = [WriteShiftLd, WriteRMW] in {
122 } // SchedRW
124 let Constraints = "$src1 = $dst", SchedRW = [WriteShift] in {
168 } // Constraints = "$src = $dst", SchedRW
171 let SchedRW = [WriteShiftLd, WriteRMW] in {
222 } // SchedRW
224 let Constraints = "$src1 = $dst", SchedRW = [WriteShift] in {
279 } // Constraints = "$src = $dst", SchedRW
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DX86ScheduleBtVer2.td77 multiclass JWriteResIntPair<X86FoldableSchedWrite SchedRW,
81 def : WriteRes<SchedRW, [ExePort]> { let Latency = Lat; }
85 def : WriteRes<SchedRW.Folded, [JLAGU, ExePort]> {
90 multiclass JWriteResFpuPair<X86FoldableSchedWrite SchedRW,
94 def : WriteRes<SchedRW, [ExePort]> { let Latency = Lat; }
98 def : WriteRes<SchedRW.Folded, [JLAGU, ExePort]> {
DX86InstrControl.td23 hasCtrlDep = 1, FPForm = SpecialFP, SchedRW = [WriteJumpLd] in {
72 let isBarrier = 1, isBranch = 1, isTerminator = 1, SchedRW = [WriteJump] in {
84 let isBranch = 1, isTerminator = 1, Uses = [EFLAGS], SchedRW = [WriteJump] in {
115 let isBranch = 1, isTerminator = 1, hasSideEffects = 0, SchedRW = [WriteJump] in {
180 let SchedRW = [WriteJump] in {
244 isCodeGenOnly = 1, SchedRW = [WriteJumpLd] in
275 let isCall = 1, Uses = [RSP], SchedRW = [WriteJump] in {
298 SchedRW = [WriteJump] in {
DX86InstrMMX.td266 let SchedRW = [WriteMove], isBitcast = 1 in {
281 } // SchedRW
289 let SchedRW = [WriteLoad] in {
295 } // SchedRW
296 let SchedRW = [WriteStore] in
302 let SchedRW = [WriteMove] in {
328 } // SchedRW
653 let SchedRW = [WriteShuffle] in {
DX86ScheduleSLM.td59 multiclass SMWriteResPair<X86FoldableSchedWrite SchedRW,
63 def : WriteRes<SchedRW, [ExePort]> { let Latency = Lat; }
67 def : WriteRes<SchedRW.Folded, [MEC_RSV, ExePort]> {
DX86SchedSandyBridge.td72 multiclass SBWriteResPair<X86FoldableSchedWrite SchedRW,
76 def : WriteRes<SchedRW, [ExePort]> { let Latency = Lat; }
80 def : WriteRes<SchedRW.Folded, [SBPort23, ExePort]> {
DX86InstrCMovSetCC.td19 isCommutable = 1, SchedRW = [WriteALU] in {
41 SchedRW = [WriteALULd, ReadAfterLd] in {
DX86InstrCompiler.td147 let SchedRW = [WriteSystem] in {
208 } // SchedRW
318 let Uses = [EFLAGS], Defs = [EFLAGS], isPseudo = 1, SchedRW = [WriteALU] in {
381 let SchedRW = [WriteMicrocoded] in {
444 } // SchedRW
596 SchedRW = [WriteALULd, WriteRMW] in {
699 SchedRW = [WriteALULd, WriteRMW], Predicates = [NotSlowIncDec] in {
736 let isCodeGenOnly = 1, SchedRW = [WriteALULd, WriteRMW] in {
757 SchedRW = [WriteALULd, WriteRMW] in {
783 SchedRW = [WriteALULd, WriteRMW], isCodeGenOnly = 1, isPseudo = 1,
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DX86InstrSSE.td454 isPseudo = 1, SchedRW = [WriteZero] in {
471 isPseudo = 1, Predicates = [NoVLX], SchedRW = [WriteZero] in {
485 isPseudo = 1, Predicates = [HasAVX, NoVLX], SchedRW = [WriteZero] in {
493 isPseudo = 1, SchedRW = [WriteZero] in {
832 let SchedRW = [WriteStore], Predicates = [HasAVX, NoVLX] in {
865 } // SchedRW
869 SchedRW = [WriteFShuffle] in {
923 let SchedRW = [WriteStore] in {
940 } // SchedRW
944 SchedRW = [WriteFShuffle] in {
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DX86SchedHaswell.td82 multiclass HWWriteResPair<X86FoldableSchedWrite SchedRW,
86 def : WriteRes<SchedRW, [ExePort]> { let Latency = Lat; }
90 def : WriteRes<SchedRW.Folded, [HWPort23, ExePort]> {
DX86InstrAVX512.td416 isPseudo = 1, Predicates = [HasAVX512], SchedRW = [WriteZero] in {
424 isPseudo = 1, Predicates = [HasVLX], SchedRW = [WriteZero] in {
2535 SchedRW = [WriteLoad] in
2550 let SchedRW = [WriteLoad] in
2560 let SchedRW = [WriteLoad] in
3287 let SchedRW = [WriteLoad] in {
3314 let SchedRW = [WriteStore], AddedComplexity = 400 in
/external/llvm/lib/Target/AMDGPU/
DSIInstrFormats.td85 let SchedRW = [Write32Bit];
281 let SchedRW = [WriteSALU] in {
343 } // let SchedRW = [WriteSALU]
354 let SchedRW = [WriteSMEM];
683 let SchedRW = [WriteLDS];
697 let SchedRW = [WriteVMEM];
710 let SchedRW = [WriteVMEM];
726 let SchedRW = [WriteVMEM];
DCIInstructions.td34 let SchedRW = [WriteDoubleAdd] in {
47 } // End SchedRW = [WriteDoubleAdd]
49 let SchedRW = [WriteQuarterRate32] in {
56 } // End SchedRW = [WriteQuarterRate32]
DSIInstructions.td485 let SchedRW = [WriteBarrier];
1218 // FIXME: Specify SchedRW for READFIRSTLANE_B32
1232 let SchedRW = [WriteQuarterRate32] in {
1288 } // End SchedRW = [WriteQuarterRate32]
1309 let SchedRW = [WriteQuarterRate32] in {
1324 } // End SchedRW = [WriteQuarterRate32]
1326 let SchedRW = [WriteDouble] in {
1335 } // End SchedRW = [WriteDouble];
1341 let SchedRW = [WriteDouble] in {
1347 } // End SchedRW = [WriteDouble]
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DSIInstrInfo.td693 let SchedRW = [WriteExport];
2056 let SchedRW = sched;
2062 let SchedRW = sched;
2068 let SchedRW = sched;
2178 let SchedRW = [Write32Bit] in {
2205 let SchedRW = [Write32Bit, WriteSALU] in {
2305 let SchedRW = sched;
2314 let SchedRW = sched;
2326 let SchedRW = sched;
/external/llvm/include/llvm/Target/
DTargetSchedule.td94 // that have a scheduling class (itinerary class or SchedRW list)
219 list<SchedReadWrite> SchedRW = schedrw;
DTarget.td438 list<SchedReadWrite> SchedRW;
/external/llvm/lib/Target/AArch64/
DAArch64InstrInfo.td2597 let SchedRW = [WriteFDiv] in {
2606 let SchedRW = [WriteFDiv] in {
2613 let SchedRW = [WriteFMul] in {