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Searched refs:Src0 (Results 1 – 25 of 46) sorted by relevance

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/external/swiftshader/third_party/subzero/src/
DIceTargetLoweringX86Base.h363 void lowerCaseCluster(const CaseCluster &Case, Operand *Src0, bool DoneCmp,
419 Operand *legalizeSrc0ForCmp(Operand *Src0, Operand *Src1);
516 void _adc(Variable *Dest, Operand *Src0) { in _adc() argument
517 AutoMemorySandboxer<> _(this, &Dest, &Src0); in _adc()
518 Context.insert<typename Traits::Insts::Adc>(Dest, Src0); in _adc()
524 void _add(Variable *Dest, Operand *Src0) { in _add() argument
525 AutoMemorySandboxer<> _(this, &Dest, &Src0); in _add()
526 Context.insert<typename Traits::Insts::Add>(Dest, Src0); in _add()
532 void _addps(Variable *Dest, Operand *Src0) { in _addps() argument
533 AutoMemorySandboxer<> _(this, &Dest, &Src0); in _addps()
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DIceTargetLoweringARM32.h213 Operand *Src0, Operand *Src1);
253 Operand *Src0, Operand *Src1);
254 CondWhenTrue lowerInt32IcmpCond(InstIcmp::ICond Condition, Operand *Src0,
256 CondWhenTrue lowerInt64IcmpCond(InstIcmp::ICond Condition, Operand *Src0,
258 CondWhenTrue lowerIcmpCond(InstIcmp::ICond Condition, Operand *Src0,
334 void _add(Variable *Dest, Variable *Src0, Operand *Src1,
336 Context.insert<InstARM32Add>(Dest, Src0, Src1, Pred);
338 void _adds(Variable *Dest, Variable *Src0, Operand *Src1,
341 Context.insert<InstARM32Add>(Dest, Src0, Src1, Pred, SetFlags);
346 void _adc(Variable *Dest, Variable *Src0, Operand *Src1,
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DIceTargetLoweringMIPS32.h166 void _add(Variable *Dest, Variable *Src0, Variable *Src1) { in _add() argument
167 Context.insert<InstMIPS32Add>(Dest, Src0, Src1); in _add()
170 void _addu(Variable *Dest, Variable *Src0, Variable *Src1) { in _addu() argument
171 Context.insert<InstMIPS32Addu>(Dest, Src0, Src1); in _addu()
174 void _and(Variable *Dest, Variable *Src0, Variable *Src1) { in _and() argument
175 Context.insert<InstMIPS32And>(Dest, Src0, Src1); in _and()
188 void _br(CfgNode *TargetTrue, CfgNode *TargetFalse, Operand *Src0, in _br() argument
190 Context.insert<InstMIPS32Br>(TargetTrue, TargetFalse, Src0, Src1, in _br()
194 void _br(CfgNode *TargetTrue, CfgNode *TargetFalse, Operand *Src0, in _br() argument
196 Context.insert<InstMIPS32Br>(TargetTrue, TargetFalse, Src0, Condition); in _br()
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DIceTargetLoweringX86BaseImpl.h804 Operand *&Src0, Operand *&Src1) {
805 if (Src0 == LoadDest && Src1 != LoadDest) {
806 Src0 = LoadSrc;
809 if (Src0 != LoadDest && Src1 == LoadDest) {
855 Operand *Src0 = Arith->getSrc(0);
857 if (canFoldLoadIntoBinaryInst(LoadSrc, LoadDest, Src0, Src1)) {
859 Arith->getDest(), Src0, Src1);
862 Operand *Src0 = Icmp->getSrc(0);
864 if (canFoldLoadIntoBinaryInst(LoadSrc, LoadDest, Src0, Src1)) {
866 Icmp->getDest(), Src0, Src1);
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DIceTargetLoweringARM32.cpp541 Operand *Src0 = Instr->getSrc(0); in genTargetHelperCallFor() local
547 Context.insert<InstCast>(CastKind, Src0_32, Src0); in genTargetHelperCallFor()
548 Src0 = Src0_32; in genTargetHelperCallFor()
574 assert(Src0->getType() == IceType_i32); in genTargetHelperCallFor()
575 Call->addArg(Src0); in genTargetHelperCallFor()
602 Operand *Src0 = Instr->getSrc(0); in genTargetHelperCallFor() local
604 const Type SrcTy = Src0->getType(); in genTargetHelperCallFor()
626 Call->addArg(Src0); in genTargetHelperCallFor()
645 Call->addArg(Src0); in genTargetHelperCallFor()
673 Context.insert<InstCast>(InstCast::Zext, Src0AsI32, Src0); in genTargetHelperCallFor()
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DIceInstARM32.h746 Variable *Src0, Operand *Src1,
750 InstARM32ThreeAddrGPR(Func, Dest, Src0, Src1, Predicate, SetFlags);
771 InstARM32ThreeAddrGPR(Cfg *Func, Variable *Dest, Variable *Src0, in InstARM32ThreeAddrGPR() argument
775 addSource(Src0); in InstARM32ThreeAddrGPR()
796 static InstARM32ThreeAddrFP *create(Cfg *Func, Variable *Dest, Variable *Src0, in create() argument
799 InstARM32ThreeAddrFP(Func, Dest, Src0, Src1); in create()
822 InstARM32ThreeAddrFP(Cfg *Func, Variable *Dest, Variable *Src0, Operand *Src1) in InstARM32ThreeAddrFP() argument
824 addSource(Src0); in InstARM32ThreeAddrFP()
847 Variable *Src0, Variable *Src1) { in create() argument
849 InstARM32ThreeAddrSignAwareFP(Func, Dest, Src0, Src1); in create()
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DIceInstMIPS32.h409 Variable *Src0) { in create() argument
411 InstMIPS32TwoAddrFPR(Func, Dest, Src0); in create()
436 InstMIPS32TwoAddrFPR(Cfg *Func, Variable *Dest, Variable *Src0) in InstMIPS32TwoAddrFPR() argument
438 addSource(Src0); in InstMIPS32TwoAddrFPR()
453 Variable *Src0) { in create() argument
455 InstMIPS32TwoAddrGPR(Func, Dest, Src0); in create()
480 InstMIPS32TwoAddrGPR(Cfg *Func, Variable *Dest, Variable *Src0) in InstMIPS32TwoAddrGPR() argument
482 addSource(Src0); in InstMIPS32TwoAddrGPR()
500 Variable *Src0, Variable *Src1) { in create() argument
502 InstMIPS32ThreeAddrFPR(Func, Dest, Src0, Src1); in create()
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DIceTargetLoweringMIPS32.cpp306 Operand *Src0 = Instr->getSrc(0); in genTargetHelperCallFor() local
316 Context.insert<InstExtractElement>(Op0, Src0, Index); in genTargetHelperCallFor()
333 Operand *Src0 = Instr->getSrc(0); in genTargetHelperCallFor() local
335 const Type SrcType = Src0->getType(); in genTargetHelperCallFor()
344 Context.insert<InstExtractElement>(Op0, Src0, Index); in genTargetHelperCallFor()
421 Operand *Src0 = Instr->getSrc(0); in genTargetHelperCallFor() local
422 const Type SrcTy = Src0->getType(); in genTargetHelperCallFor()
435 Context.insert<InstExtractElement>(Op, Src0, Index); in genTargetHelperCallFor()
475 Call->addArg(Src0); in genTargetHelperCallFor()
504 Call->addArg(Src0); in genTargetHelperCallFor()
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DIceInstARM32.cpp1168 const Operand *Src0 = getSrc(0); in emitIAS() local
1170 Type SrcTy = Src0->getType(); in emitIAS()
1184 Asm->vqmovn2(typeElementType(DestTy), Dest, Src0, Src1, Unsigned, in emitIAS()
1190 Asm->vqmovn2(typeElementType(DestTy), Dest, Src0, Src1, Unsigned, in emitIAS()
1196 Asm->vqmovn2(typeElementType(DestTy), Dest, Src0, Src1, Unsigned, in emitIAS()
1207 const Operand *Src0 = getSrc(0); in emitIAS() local
1208 Type SrcTy = Src0->getType(); in emitIAS()
1233 const Operand *Src0 = getSrc(0); in emitIAS() local
1235 Type SrcTy = Src0->getType(); in emitIAS()
1241 Asm->vmlap(typeElementType(SrcTy), Dest, Src0, Src1); in emitIAS()
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DIceTargetLowering.h504 Operand *Src0, Operand *Src1);
566 auto *Src0 = thunk0(); in applyToThunkedArgs() local
567 return insertScalarInstruction(Res, Src0); in applyToThunkedArgs()
575 auto *Src0 = thunk0(); in applyToThunkedArgs() local
577 return insertScalarInstruction(Res, Src0, Src1); in applyToThunkedArgs()
585 auto *Src0 = thunk0(); in applyToThunkedArgs() local
588 return insertScalarInstruction(Res, Src0, Src1, Src2); in applyToThunkedArgs()
DIceTargetLoweringARM32.def27 // vcCC0_V Cmp0, Src0, Src1 /* only if CC0_V != none */
28 // vcCC1_V Cmp1, Src1, Src0 /* only if CC1_V != none */
32 // If INV_V = true, then Src0 and Src1 should be swapped.
DIceCfg.cpp1336 const CfgVector<const Inst *> &Insts, Variable **Src0, in findAllExtracts() argument
1340 *Src0 = nullptr; in findAllExtracts()
1375 if (*Src0 == nullptr) { in findAllExtracts()
1377 *Src0 = Src; in findAllExtracts()
1381 if (*Src0 != Src) { in findAllExtracts()
1384 } else if (Src != *Src0 && Src != *Src1) { in findAllExtracts()
1397 assert(*Src0 != nullptr); in findAllExtracts()
1403 *Src1 = *Src0; in findAllExtracts()
1464 Variable *Src0; in materializeVectorShuffles() local
1467 VMetadata.get(), Inserts, &Src0, in materializeVectorShuffles()
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DIceInstX86BaseImpl.h253 InstImpl<TraitsType>::InstX86Icmp::InstX86Icmp(Cfg *Func, Operand *Src0, in InstX86Icmp() argument
256 this->addSource(Src0); in InstX86Icmp()
261 InstImpl<TraitsType>::InstX86Ucomiss::InstX86Ucomiss(Cfg *Func, Operand *Src0, in InstX86Ucomiss() argument
264 this->addSource(Src0); in InstX86Ucomiss()
959 const Cfg *Func, Type DispatchTy, const Variable *Dest, const Operand *Src0, in emitIASThreeOpImmOps() argument
967 if (const auto *SrcVar = llvm::dyn_cast<Variable>(Src0)) { in emitIASThreeOpImmOps()
975 } else if (const auto *Mem = llvm::dyn_cast<X86OperandMem>(Src0)) { in emitIASThreeOpImmOps()
1290 Operand *Src0 = this->getSrc(0); in emit() local
1292 const auto SrcReg = llvm::cast<Variable>(Src0)->getRegNum(); in emit()
1295 switch (Src0->getType()) { in emit()
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DIceConverter.cpp346 Ice::Operand *Src0 = convertOperand(Instr, 0); in convertArithInstruction() local
349 return Ice::InstArithmetic::create(Func.get(), Opcode, Dest, Src0, Src1); in convertArithInstruction()
406 Ice::Operand *Src0 = convertOperand(Instr, 0); in convertICmpInstruction() local
446 return Ice::InstIcmp::create(Func.get(), Cond, Dest, Src0, Src1); in convertICmpInstruction()
450 Ice::Operand *Src0 = convertOperand(Instr, 0); in convertFCmpInstruction() local
510 return Ice::InstFcmp::create(Func.get(), Cond, Dest, Src0, Src1); in convertFCmpInstruction()
DIceInstMIPS32.cpp165 auto *Src0 = llvm::cast<Constant>(getSrc(0)); in emit() local
166 if (auto *CR = llvm::dyn_cast<ConstantRelocatable>(Src0)) { in emit()
172 Src0->emit(Func); in emit()
183 const CfgNode *TargetFalse, Operand *Src0, in InstMIPS32Br() argument
187 addSource(Src0); in InstMIPS32Br()
191 const CfgNode *TargetFalse, Operand *Src0, in InstMIPS32Br() argument
196 addSource(Src0); in InstMIPS32Br()
/external/swiftshader/third_party/subzero/unittest/AssemblerX8664/
DControlFlow.cpp17 #define TestJ(C, Near, Dest, Src0, Value0, Src1, Value1) \ in TEST_F() argument
20 "(" #C ", " #Near ", " #Dest ", " #Src0 ", " #Value0 ", " #Src1 \ in TEST_F()
24 __ mov(IceType_i32, Encoded_GPR_##Src0(), Immediate(Value0)); \ in TEST_F()
27 __ cmp(IceType_i32, Encoded_GPR_##Src0(), Encoded_GPR_##Src1()); \ in TEST_F()
33 ASSERT_EQ(Value0, test.Src0()) << TestString; \ in TEST_F()
39 #define TestImpl(Dst, Src0, Src1) \ in TEST_F() argument
41 TestJ(o, Near, Dst, Src0, 0x80000000ul, Src1, 0x1ul); \ in TEST_F()
42 TestJ(o, Far, Dst, Src0, 0x80000000ul, Src1, 0x1ul); \ in TEST_F()
43 TestJ(no, Near, Dst, Src0, 0x1ul, Src1, 0x1ul); \ in TEST_F()
44 TestJ(no, Far, Dst, Src0, 0x1ul, Src1, 0x1ul); \ in TEST_F()
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DDataMov.cpp422 #define TestRegReg(C, Dest, IsTrue, Src0, Value0, Src1, Value1) \ in TEST_F() argument
425 "(" #C ", " #Dest ", " #IsTrue ", " #Src0 ", " #Value0 ", " #Src1 \ in TEST_F()
427 __ mov(IceType_i32, Encoded_GPR_##Src0(), Immediate(Value0)); \ in TEST_F()
430 __ cmp(IceType_i32, Encoded_GPR_##Src0(), Encoded_GPR_##Src1()); \ in TEST_F()
441 #define TestRegAddr(C, Dest, IsTrue, Src0, Value0, Value1) \ in TEST_F() argument
444 "(" #C ", " #Dest ", " #IsTrue ", " #Src0 ", " #Value0 \ in TEST_F()
448 __ mov(IceType_i32, Encoded_GPR_##Src0(), Immediate(Value0)); \ in TEST_F()
450 __ cmp(IceType_i32, Encoded_GPR_##Src0(), dwordAddress(T0)); \ in TEST_F()
462 #define TestValue(C, Dest, IsTrue, Src0, Value0, Src1, Value1) \ in TEST_F() argument
464 TestRegReg(C, Dest, IsTrue, Src0, Value0, Src1, Value1); \ in TEST_F()
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DGPRArith.cpp33 #define TestSetCC(C, Dest, IsTrue, Src0, Value0, Src1, Value1) \ in TEST_F() argument
36 "(" #C ", " #Dest ", " #IsTrue ", " #Src0 ", " #Value0 ", " #Src1 \ in TEST_F()
40 __ mov(IceType_i32, Encoded_GPR_##Src0(), Immediate(Value0)); \ in TEST_F()
42 __ cmp(IceType_i32, Encoded_GPR_##Src0(), Encoded_GPR_##Src1()); \ in TEST_F()
57 #define TestImpl(Dest, Src0, Src1) \ in TEST_F() argument
59 TestSetCC(o, Dest, 1u, Src0, 0x80000000u, Src1, 0x1u); \ in TEST_F()
60 TestSetCC(o, Dest, 0u, Src0, 0x1u, Src1, 0x10000000u); \ in TEST_F()
61 TestSetCC(no, Dest, 1u, Src0, 0x1u, Src1, 0x10000000u); \ in TEST_F()
62 TestSetCC(no, Dest, 0u, Src0, 0x80000000u, Src1, 0x1u); \ in TEST_F()
63 TestSetCC(b, Dest, 1u, Src0, 0x1, Src1, 0x80000000u); \ in TEST_F()
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/external/llvm/lib/Target/AMDGPU/
DSIShrinkInstructions.cpp139 MachineOperand &Src0 = MI.getOperand(Src0Idx); in foldImmediates() local
143 if (Src0.isImm() && in foldImmediates()
144 TII->isLiteralConstant(Src0, TII->getOpSize(MI, Src0Idx))) in foldImmediates()
150 if (Src0.isReg() && !isVGPR(&Src0, TRI, MRI)) in foldImmediates()
154 if (Src0.isReg() && MRI.hasOneUse(Src0.getReg())) { in foldImmediates()
155 unsigned Reg = Src0.getReg(); in foldImmediates()
162 Src0.ChangeToImmediate(MovSrc.getImm()); in foldImmediates()
276 const MachineOperand &Src0 = MI.getOperand(1); in runOnMachineFunction() local
283 Src0.isReg()) { in runOnMachineFunction()
284 MRI.setRegAllocationHint(Dest.getReg(), 0, Src0.getReg()); in runOnMachineFunction()
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DR600ExpandSpecialInstrs.cpp222 unsigned Src0 = BMI->getOperand( in runOnMachineFunction() local
228 (void) Src0; in runOnMachineFunction()
230 if ((TRI.getEncodingValue(Src0) & 0xff) < 127 && in runOnMachineFunction()
232 assert(TRI.getHWRegChan(Src0) == TRI.getHWRegChan(Src1)); in runOnMachineFunction()
274 unsigned Src0 = MI.getOperand( in runOnMachineFunction() local
287 Src0 = TRI.getSubReg(Src0, SubRegIndex); in runOnMachineFunction()
293 Src1 = TRI.getSubReg(Src0, SubRegIndex1); in runOnMachineFunction()
294 Src0 = TRI.getSubReg(Src0, SubRegIndex0); in runOnMachineFunction()
328 TII->buildDefaultInstruction(MBB, I, Opcode, DstReg, Src0, Src1); in runOnMachineFunction()
DSIInstrInfo.cpp889 unsigned Src0 = MI.getOperand(1).getReg(); in expandPostRAPseudo() local
894 .addReg(RI.getSubReg(Src0, AMDGPU::sub0)) in expandPostRAPseudo()
899 .addReg(RI.getSubReg(Src0, AMDGPU::sub1)) in expandPostRAPseudo()
954 MachineOperand &Src0 = MI.getOperand(Src0Idx); in commuteInstructionImpl() local
955 if (!Src0.isReg()) in commuteInstructionImpl()
978 if (!isLegalRegOperand(MRI, InstrDesc.OpInfo[Src1Idx], Src0)) in commuteInstructionImpl()
1007 unsigned Reg = Src0.getReg(); in commuteInstructionImpl()
1008 unsigned SubReg = Src0.getSubReg(); in commuteInstructionImpl()
1010 Src0.ChangeToImmediate(Src1.getImm()); in commuteInstructionImpl()
1239 MachineOperand *Src0 = getNamedOperand(UseMI, AMDGPU::OpName::src0); in FoldImmediate() local
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/external/llvm/lib/Target/AArch64/
DAArch64AdvSIMDScalarPass.cpp306 unsigned Src0 = 0, SubReg0; in transformInstruction() local
317 Src0 = MOSrc0->getReg(); in transformInstruction()
349 if (!Src0) { in transformInstruction()
351 Src0 = MRI->createVirtualRegister(&AArch64::FPR64RegClass); in transformInstruction()
352 insertCopy(TII, MI, Src0, OrigSrc0, KillSrc0); in transformInstruction()
371 .addReg(Src0, getKillRegState(KillSrc0), SubReg0) in transformInstruction()
/external/swiftshader/third_party/subzero/unittest/AssemblerX8632/
DGPRArith.cpp48 #define TestSetCC(C, Src0, Value0, Src1, Value1, Dest, IsTrue) \ in TEST_F() argument
52 __ mov(IceType_i32, GPRRegister::Encoded_Reg_##Src0, Immediate(Value0)); \ in TEST_F()
54 __ cmp(IceType_i32, GPRRegister::Encoded_Reg_##Src0, \ in TEST_F()
66 << "(" #C ", " #Src0 ", " #Value0 ", " #Src1 ", " #Value1 ", " #Dest \ in TEST_F()
69 << "(" #C ", " #Src0 ", " #Value0 ", " #Src1 ", " #Value1 ", " #Dest \ in TEST_F()
678 #define TestImplRegReg(Inst0, Inst1, Dst0, Dst1, Value0, Src0, Src1, Value1, \ in TEST_F() argument
684 "(" #Inst0 ", " #Inst1 ", " #Dst0 ", " #Dst1 ", " #Value0 ", " #Src0 \ in TEST_F()
690 __ mov(IceType_i##Size, GPRRegister::Encoded_Reg_##Src0, \ in TEST_F()
695 GPRRegister::Encoded_Reg_##Src0); \ in TEST_F()
776 #define TestImplAddrReg(Inst0, Inst1, Value0, Src0, Src1, Value1, Op, Size) \ in TEST_F() argument
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DControlFlow.cpp18 #define TestJ(C, Near, Src0, Value0, Src1, Value1, Dest) \ in TEST_F() argument
22 __ mov(IceType_i32, GPRRegister::Encoded_Reg_##Src0, Immediate(Value0)); \ in TEST_F()
25 __ cmp(IceType_i32, GPRRegister::Encoded_Reg_##Src0, \ in TEST_F()
32 EXPECT_EQ(Value0, test.Src0()) << "Br_" #C ", " #Near; \ in TEST_F()
/external/v8/src/asmjs/
Dasm-typer.cc2013 #define BINOP_OVERLOAD(Src0, Src1, Dest) \ in ValidateMultiplicativeExpression() argument
2015 if (left_type->IsA(AsmType::Src0()) && right_type->IsA(AsmType::Src1())) { \ in ValidateMultiplicativeExpression()
2114 #define BINOP_OVERLOAD(Src0, Src1, Dest) \ in ValidateShiftExpression() argument
2116 if (left_type->IsA(AsmType::Src0()) && right_type->IsA(AsmType::Src1())) { \ in ValidateShiftExpression()
2148 #define CMPOP_OVERLOAD(Src0, Src1, Dest) \ in ValidateRelationalExpression() argument
2150 if (left_type->IsA(AsmType::Src0()) && right_type->IsA(AsmType::Src1())) { \ in ValidateRelationalExpression()
2197 #define CMPOP_OVERLOAD(Src0, Src1, Dest) \ in ValidateEqualityExpression() argument
2199 if (left_type->IsA(AsmType::Src0()) && right_type->IsA(AsmType::Src1())) { \ in ValidateEqualityExpression()
2238 #define BINOP_OVERLOAD(Src0, Src1, Dest) \ in ValidateBitwiseANDExpression() argument
2240 if (left_type->IsA(AsmType::Src0()) && right_type->IsA(AsmType::Src1())) { \ in ValidateBitwiseANDExpression()
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