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Searched refs:Src2 (Results 1 – 25 of 33) sorted by relevance

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/external/swiftshader/third_party/LLVM/lib/ExecutionEngine/Interpreter/
DExecution.cpp50 Dest.TY##Val = Src1.TY##Val OP Src2.TY##Val; \
54 GenericValue Src2, Type *Ty) { in executeFAddInst() argument
65 GenericValue Src2, Type *Ty) { in executeFSubInst() argument
76 GenericValue Src2, Type *Ty) { in executeFMulInst() argument
87 GenericValue Src2, Type *Ty) { in executeFDivInst() argument
98 GenericValue Src2, Type *Ty) { in executeFRemInst() argument
101 Dest.FloatVal = fmod(Src1.FloatVal, Src2.FloatVal); in executeFRemInst()
104 Dest.DoubleVal = fmod(Src1.DoubleVal, Src2.DoubleVal); in executeFRemInst()
114 Dest.IntVal = APInt(1,Src1.IntVal.OP(Src2.IntVal)); \
124 (void*)(intptr_t)Src2.PointerVal); \
[all …]
/external/llvm/lib/ExecutionEngine/Interpreter/
DExecution.cpp52 Dest.TY##Val = Src1.TY##Val OP Src2.TY##Val; \
56 GenericValue Src2, Type *Ty) { in executeFAddInst() argument
67 GenericValue Src2, Type *Ty) { in executeFSubInst() argument
78 GenericValue Src2, Type *Ty) { in executeFMulInst() argument
89 GenericValue Src2, Type *Ty) { in executeFDivInst() argument
100 GenericValue Src2, Type *Ty) { in executeFRemInst() argument
103 Dest.FloatVal = fmod(Src1.FloatVal, Src2.FloatVal); in executeFRemInst()
106 Dest.DoubleVal = fmod(Src1.DoubleVal, Src2.DoubleVal); in executeFRemInst()
116 Dest.IntVal = APInt(1,Src1.IntVal.OP(Src2.IntVal)); \
121 assert(Src1.AggregateVal.size() == Src2.AggregateVal.size()); \
[all …]
/external/llvm/lib/Target/AMDGPU/
DSIShrinkInstructions.cpp84 const MachineOperand *Src2 = TII->getNamedOperand(MI, AMDGPU::OpName::src2); in canShrink() local
91 if (Src2) { in canShrink()
96 if (!isVGPR(Src2, TRI, MRI) || in canShrink()
348 const MachineOperand *Src2 = in runOnMachineFunction() local
350 if (!Src2->isReg()) in runOnMachineFunction()
352 unsigned SReg = Src2->getReg(); in runOnMachineFunction()
386 const MachineOperand *Src2 = in runOnMachineFunction() local
388 if (Src2) { in runOnMachineFunction()
391 Inst32.addOperand(*Src2); in runOnMachineFunction()
396 copyFlagsToImplicitVCC(*Inst32, *Src2); in runOnMachineFunction()
DSIInstrInfo.cpp1241 MachineOperand *Src2 = getNamedOperand(UseMI, AMDGPU::OpName::src2); in FoldImmediate() local
1249 if (!Src2->isReg() || RI.isSGPRClass(MRI->getRegClass(Src2->getReg()))) in FoldImmediate()
1289 if (Src2->isReg() && Src2->getReg() == Reg) { in FoldImmediate()
1316 Src2->ChangeToImmediate(Imm); in FoldImmediate()
1435 const MachineOperand *Src2 = getNamedOperand(MI, AMDGPU::OpName::src2); in convertToThreeAddress() local
1444 .addOperand(*Src2) in convertToThreeAddress()
1762 const MachineOperand &Src2 = MI.getOperand(Src2Idx); in verifyInstruction() local
1763 if (Src0.isReg() && Src1.isReg() && Src2.isReg()) { in verifyInstruction()
1765 !compareMachineOp(Src0, Src2)) { in verifyInstruction()
/external/llvm/lib/Target/Hexagon/
DHexagonGenMux.cpp97 const MachineOperand &Src2) const;
176 const MachineOperand &Src2) const { in getMuxOpcode()
177 bool IsReg1 = Src1.isReg(), IsReg2 = Src2.isReg(); in getMuxOpcode()
185 if (Src2.isImm() && isInt<8>(Src2.getImm())) in getMuxOpcode()
266 MachineOperand *Src1 = &Def1.getOperand(2), *Src2 = &Def2.getOperand(2); in genMuxInBlock() local
268 unsigned SR2 = Src2->isReg() ? Src2->getReg() : 0; in genMuxInBlock()
284 MachineOperand *SrcT = (MinX == CI.TrueX) ? Src1 : Src2; in genMuxInBlock()
285 MachineOperand *SrcF = (MinX == CI.FalseX) ? Src1 : Src2; in genMuxInBlock()
DHexagonPeephole.cpp160 MachineOperand &Src2 = MI.getOperand(2); in runOnMachineFunction() local
164 unsigned SrcReg = Src2.getReg(); in runOnMachineFunction()
177 MachineOperand &Src2 = MI.getOperand(2); in runOnMachineFunction() local
178 if (Src2.getImm() != 32) in runOnMachineFunction()
/external/llvm/lib/Target/SystemZ/
DSystemZSelectionDAGInfo.cpp150 SDValue Src1, SDValue Src2, uint64_t Size) { in emitCLC() argument
162 return DAG.getNode(SystemZISD::CLC_LOOP, DL, VTs, Chain, Src1, Src2, in emitCLC()
165 return DAG.getNode(SystemZISD::CLC, DL, VTs, Chain, Src1, Src2, in emitCLC()
185 SDValue Src2, SDValue Size, MachinePointerInfo Op1PtrInfo, in EmitTargetCodeForMemcmp() argument
190 Chain = emitCLC(DAG, DL, Chain, Src1, Src2, Bytes); in EmitTargetCodeForMemcmp()
236 SDValue Src2, MachinePointerInfo Op1PtrInfo, in EmitTargetCodeForStrcmp() argument
239 SDValue Unused = DAG.getNode(SystemZISD::STRCMP, DL, VTs, Chain, Src1, Src2, in EmitTargetCodeForStrcmp()
DSystemZSelectionDAGInfo.h41 SDValue Src1, SDValue Src2, SDValue Size,
57 SDValue Src1, SDValue Src2,
DSystemZISelLowering.cpp3220 SDValue Src2 = Node->getVal(); in lowerATOMIC_LOAD_OP() local
3227 if (auto *Const = dyn_cast<ConstantSDNode>(Src2)) { in lowerATOMIC_LOAD_OP()
3229 Src2 = DAG.getConstant(-Const->getSExtValue(), DL, Src2.getValueType()); in lowerATOMIC_LOAD_OP()
3253 Src2 = DAG.getNode(ISD::SHL, DL, WideVT, Src2, in lowerATOMIC_LOAD_OP()
3257 Src2 = DAG.getNode(ISD::OR, DL, WideVT, Src2, in lowerATOMIC_LOAD_OP()
3262 SDValue Ops[] = { ChainIn, AlignedAddr, Src2, BitShift, NegBitShift, in lowerATOMIC_LOAD_OP()
3287 SDValue Src2 = Node->getVal(); in lowerATOMIC_LOAD_SUB() local
3289 SDLoc DL(Src2); in lowerATOMIC_LOAD_SUB()
3291 if (auto *Op2 = dyn_cast<ConstantSDNode>(Src2)) { in lowerATOMIC_LOAD_SUB()
3300 Src2); in lowerATOMIC_LOAD_SUB()
[all …]
/external/syslinux/gnu-efi/gnu-efi-3.0/lib/
Ddpath.c120 IN EFI_DEVICE_PATH *Src2 in AppendDevicePath() argument
136 ASSERT (!IsDevicePathUnpacked (Src2)); in AppendDevicePath()
137 return DuplicateDevicePath (Src2); in AppendDevicePath()
140 if (!Src2) { in AppendDevicePath()
158 Src2Size = DevicePathSize(Src2); in AppendDevicePath()
174 CopyMem(DstPos, Src2, Src2Size); in AppendDevicePath()
193 IN EFI_DEVICE_PATH *Src2 in AppendDevicePathNode() argument
206 Length = DevicePathNodeLength(Src2); in AppendDevicePathNode()
212 CopyMem (Temp, Src2, Length); in AppendDevicePathNode()
/external/llvm/lib/Target/X86/
DX86FixupLEAs.cpp378 const MachineOperand &Src2 = MI.getOperand(SrcR1 == DstR ? 3 : 1); in processInstructionForSLM() local
382 .addOperand(Src2); in processInstructionForSLM()
DX86ISelLowering.cpp17416 SDValue Src2 = Op.getOperand(2); in LowerINTRINSIC_WO_CHAIN() local
17419 return getScalarMaskingNode(DAG.getNode(IntrData->Opc0, dl, VT, Src1, Src2), in LowerINTRINSIC_WO_CHAIN()
17424 SDValue Src2 = Op.getOperand(2); in LowerINTRINSIC_WO_CHAIN() local
17433 return getScalarMaskingNode(DAG.getNode(Opc, dl, VT, Src1, Src2, in LowerINTRINSIC_WO_CHAIN()
17440 return getScalarMaskingNode(DAG.getNode(IntrData->Opc0, dl, VT, Src1, Src2, in LowerINTRINSIC_WO_CHAIN()
17447 SDValue Src2 = Op.getOperand(2); in LowerINTRINSIC_WO_CHAIN() local
17452 Src2 = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, Src2); in LowerINTRINSIC_WO_CHAIN()
17464 Src1, Src2, Rnd), in LowerINTRINSIC_WO_CHAIN()
17469 return getVectorMaskingNode(DAG.getNode(IntrData->Opc0, dl, VT,Src1,Src2), in LowerINTRINSIC_WO_CHAIN()
17474 SDValue Src2 = Op.getOperand(2); in LowerINTRINSIC_WO_CHAIN() local
[all …]
DX86InstrInfo.cpp2695 unsigned Src2 = MI.getOperand(2).getReg(); in convertToThreeAddressWithLEA() local
2699 if (Src == Src2) { in convertToThreeAddressWithLEA()
2713 .addReg(Src2, getKillRegState(isKill2)); in convertToThreeAddressWithLEA()
2717 LV->replaceKillInstruction(Src2, MI, *InsMI2); in convertToThreeAddressWithLEA()
2926 const MachineOperand &Src2 = MI.getOperand(2); in convertToThreeAddress() local
2930 if (!classifyLEAReg(MI, Src2, Opc, /*AllowSP=*/ false, in convertToThreeAddress()
2947 if (LV && Src2.isKill()) in convertToThreeAddress()
2957 unsigned Src2 = MI.getOperand(2).getReg(); in convertToThreeAddress() local
2961 Src.getReg(), Src.isKill(), Src2, isKill2); in convertToThreeAddress()
2970 LV->replaceKillInstruction(Src2, MI, *NewMI); in convertToThreeAddress()
/external/llvm/lib/Target/Sparc/
DSparcAsmPrinter.cpp130 MCOperand &RS1, MCOperand &Src2, MCOperand &RD, in EmitBinary() argument
137 Inst.addOperand(Src2); in EmitBinary()
/external/swiftshader/third_party/subzero/src/
DIceTargetLowering.h587 auto *Src2 = thunk2(); in applyToThunkedArgs() local
588 return insertScalarInstruction(Res, Src0, Src1, Src2); in applyToThunkedArgs()
DIceInstMIPS32.cpp291 Operand *Src2) in InstMIPS32Mov() argument
298 if (Dest->getType() == IceType_f64 && Src2 != nullptr) { in InstMIPS32Mov()
300 addSource(Src2); in InstMIPS32Mov()
DIceInstARM32.h877 Variable *Src1, Variable *Src2, in create() argument
880 InstARM32FourAddrGPR(Func, Dest, Src0, Src1, Src2, Predicate); in create()
902 Variable *Src1, Variable *Src2, in InstARM32FourAddrGPR() argument
907 addSource(Src2); in InstARM32FourAddrGPR()
DIceInstMIPS32.h1299 Operand *Src2) { in create() argument
1301 InstMIPS32Mov(Func, Dest, Src, Src2); in create()
1316 InstMIPS32Mov(Cfg *Func, Variable *Dest, Operand *Src, Operand *Src2);
DIceInstX86BaseImpl.h278 Operand *Src2) in InstX86Test() argument
281 this->addSource(Src2); in InstX86Test()
1429 const Operand *Src2 = this->getSrc(2); in emitIAS() local
1431 emitIASGPRShiftDouble(Func, Dest, Src1, Src2, Emitter); in emitIAS()
1467 const Operand *Src2 = this->getSrc(2); in emitIAS() local
1469 emitIASGPRShiftDouble(Func, Dest, Src1, Src2, Emitter); in emitIAS()
DIceInstX86Base.h2628 static InstX86Icmp *create(Cfg *Func, Operand *Src1, Operand *Src2) { in create()
2629 return new (Func->allocate<InstX86Icmp>()) InstX86Icmp(Func, Src1, Src2); in create()
2639 InstX86Icmp(Cfg *Func, Operand *Src1, Operand *Src2);
2649 static InstX86Ucomiss *create(Cfg *Func, Operand *Src1, Operand *Src2) { in create()
2651 InstX86Ucomiss(Func, Src1, Src2); in create()
2661 InstX86Ucomiss(Cfg *Func, Operand *Src1, Operand *Src2);
/external/swiftshader/third_party/LLVM/lib/Target/X86/
DX86InstrInfo.cpp1383 unsigned Src2 = MI->getOperand(2).getReg(); in convertToThreeAddressWithLEA() local
1387 if (Src == Src2) { in convertToThreeAddressWithLEA()
1399 .addReg(Src2, getKillRegState(isKill2)); in convertToThreeAddressWithLEA()
1403 LV->replaceKillInstruction(Src2, MI, InsMI2); in convertToThreeAddressWithLEA()
1610 unsigned Src2 = MI->getOperand(2).getReg(); in convertToThreeAddress() local
1614 if (TargetRegisterInfo::isVirtualRegister(Src2) && in convertToThreeAddress()
1615 !MF.getRegInfo().constrainRegClass(Src2, RC)) in convertToThreeAddress()
1621 Src, isKill, Src2, isKill2); in convertToThreeAddress()
1623 LV->replaceKillInstruction(Src2, MI, NewMI); in convertToThreeAddress()
1631 unsigned Src2 = MI->getOperand(2).getReg(); in convertToThreeAddress() local
[all …]
/external/syslinux/efi32/include/efi/
Defilib.h684 IN EFI_DEVICE_PATH *Src2
690 IN EFI_DEVICE_PATH *Src2
/external/syslinux/gnu-efi/gnu-efi-3.0/inc/
Defilib.h684 IN EFI_DEVICE_PATH *Src2
690 IN EFI_DEVICE_PATH *Src2
/external/syslinux/efi64/include/efi/
Defilib.h684 IN EFI_DEVICE_PATH *Src2
690 IN EFI_DEVICE_PATH *Src2
/external/swiftshader/third_party/LLVM/lib/CodeGen/SelectionDAG/
DSelectionDAGBuilder.cpp2788 SDValue Src2 = getValue(I.getOperand(1)); in visitShuffleVector() local
2807 setValue(&I, DAG.getVectorShuffle(VT, getCurDebugLoc(), Src1, Src2, in visitShuffleVector()
2820 VT, Src1, Src2)); in visitShuffleVector()
2827 bool Src2U = Src2.getOpcode() == ISD::UNDEF; in visitShuffleVector()
2833 MOps2[0] = Src2; in visitShuffleVector()
2838 Src2 = Src2U ? DAG.getUNDEF(VT) : DAG.getNode(ISD::CONCAT_VECTORS, in visitShuffleVector()
2852 setValue(&I, DAG.getVectorShuffle(VT, getCurDebugLoc(), Src1, Src2, in visitShuffleVector()
2912 SDValue &Src = Input == 0 ? Src1 : Src2; in visitShuffleVector()
2932 setValue(&I, DAG.getVectorShuffle(VT, getCurDebugLoc(), Src1, Src2, in visitShuffleVector()
2956 EltVT, Src2, in visitShuffleVector()

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