| /external/llvm/lib/Target/AMDGPU/ |
| D | SIFixSGPRCopies.cpp | 135 const TargetRegisterClass *SrcRC = in getCopyRegClasses() local
148 return std::make_pair(SrcRC, DstRC); in getCopyRegClasses()
151 static bool isVGPRToSGPRCopy(const TargetRegisterClass *SrcRC, in isVGPRToSGPRCopy() argument
154 return TRI.isSGPRClass(DstRC) && TRI.hasVGPRs(SrcRC); in isVGPRToSGPRCopy()
157 static bool isSGPRToVGPRCopy(const TargetRegisterClass *SrcRC, in isSGPRToVGPRCopy() argument
160 return TRI.isSGPRClass(SrcRC) && TRI.hasVGPRs(DstRC); in isSGPRToVGPRCopy()
193 const TargetRegisterClass *SrcRC, *DstRC; in foldVGPRCopyIntoRegSequence() local
194 std::tie(SrcRC, DstRC) = getCopyRegClasses(CopyUse, *TRI, MRI); in foldVGPRCopyIntoRegSequence()
196 if (!isSGPRToVGPRCopy(SrcRC, DstRC, *TRI)) in foldVGPRCopyIntoRegSequence()
220 const TargetRegisterClass *SrcRC = MRI.getRegClass(SrcReg); in foldVGPRCopyIntoRegSequence() local
[all …]
|
| D | SILowerI1Copies.cpp | 103 const TargetRegisterClass *SrcRC = MRI.getRegClass(Src.getReg()); in runOnMachineFunction() local
106 TRI->getCommonSubClass(SrcRC, &AMDGPU::SGPR_64RegClass)) { in runOnMachineFunction()
133 SrcRC == &AMDGPU::VReg_1RegClass) { in runOnMachineFunction()
|
| D | SIRegisterInfo.h | 137 const TargetRegisterClass *SrcRC,
|
| D | SIRegisterInfo.cpp | 810 const TargetRegisterClass *SrcRC, in shouldRewriteCopySrc() argument
828 return getCommonSubClass(DefRC, SrcRC) != nullptr; in shouldRewriteCopySrc()
|
| /external/llvm/lib/Target/NVPTX/ |
| D | NVPTXInstrInfo.cpp | 39 const TargetRegisterClass *SrcRC = MRI.getRegClass(SrcReg); in copyPhysReg() local
41 if (DestRC->getSize() != SrcRC->getSize()) in copyPhysReg()
50 Op = (SrcRC == &NVPTX::Int32RegsRegClass ? NVPTX::IMOV32rr in copyPhysReg()
53 Op = (SrcRC == &NVPTX::Int64RegsRegClass ? NVPTX::IMOV64rr in copyPhysReg()
56 Op = (SrcRC == &NVPTX::Float32RegsRegClass ? NVPTX::FMOV32rr in copyPhysReg()
59 Op = (SrcRC == &NVPTX::Float64RegsRegClass ? NVPTX::FMOV64rr in copyPhysReg()
|
| /external/llvm/lib/CodeGen/ |
| D | TargetRegisterInfo.cpp | 292 const TargetRegisterClass *SrcRC, in shareSameRegisterFile() argument
295 if (DefRC == SrcRC) in shareSameRegisterFile()
301 return TRI.getCommonSuperRegClass(SrcRC, SrcSubReg, DefRC, DefSubReg, in shareSameRegisterFile()
309 std::swap(DefRC, SrcRC); in shareSameRegisterFile()
314 return TRI.getMatchingSuperRegClass(SrcRC, DefRC, SrcSubReg) != nullptr; in shareSameRegisterFile()
317 return TRI.getCommonSubClass(DefRC, SrcRC) != nullptr; in shareSameRegisterFile()
322 const TargetRegisterClass *SrcRC, in shouldRewriteCopySrc() argument
325 return shareSameRegisterFile(*this, DefRC, DefSubReg, SrcRC, SrcSubReg); in shouldRewriteCopySrc()
|
| D | DetectDeadLanes.cpp | 161 const TargetRegisterClass *SrcRC = MRI.getRegClass(SrcReg); in isCrossCopy() local
162 if (DstRC == SrcRC) in isCrossCopy()
187 return !TRI.getCommonSuperRegClass(SrcRC, SrcSubIdx, DstRC, DstSubIdx, PreA, in isCrossCopy()
190 return !TRI.getMatchingSuperRegClass(SrcRC, DstRC, SrcSubIdx); in isCrossCopy()
192 return !TRI.getMatchingSuperRegClass(DstRC, SrcRC, DstSubIdx); in isCrossCopy()
193 return !TRI.getCommonSubClass(SrcRC, DstRC); in isCrossCopy()
|
| D | RegisterCoalescer.cpp | 352 const TargetRegisterClass *SrcRC = MRI.getRegClass(Src); in setRegisters() local
361 NewRC = TRI.getCommonSuperRegClass(SrcRC, SrcSub, DstRC, DstSub, in setRegisters()
368 NewRC = TRI.getMatchingSuperRegClass(DstRC, SrcRC, DstSub); in setRegisters()
372 NewRC = TRI.getMatchingSuperRegClass(SrcRC, DstRC, SrcSub); in setRegisters()
375 NewRC = TRI.getCommonSubClass(DstRC, SrcRC); in setRegisters()
390 CrossClass = NewRC != DstRC || NewRC != SrcRC; in setRegisters()
1353 auto SrcRC = MRI->getRegClass(CP.getSrcReg()); in joinCopy() local
1359 std::swap(SrcRC, DstRC); in joinCopy()
1361 if (!TRI->shouldCoalesce(CopyMI, SrcRC, SrcIdx, DstRC, DstIdx, in joinCopy()
|
| /external/swiftshader/third_party/LLVM/lib/Target/Mips/ |
| D | MipsInstrFormats.td | 273 RegisterClass DstRC, RegisterClass SrcRC> :
274 FFR<0x11, funct, fmt, (outs DstRC:$fd), (ins SrcRC:$fs),
281 RegisterClass DstRC, RegisterClass SrcRC, SDNode OpNode> :
282 FFR<0x11, funct, fmt, (outs DstRC:$fd), (ins SrcRC:$fs),
284 [(set DstRC:$fd, (OpNode SrcRC:$fs))]> {
|
| /external/llvm/lib/Target/Mips/ |
| D | MicroMips32r6InstrInfo.td | 669 RegisterOperand SrcRC> {
670 dag InOperandList = (ins SrcRC:$rt, uimm3:$sel);
678 string opstr, RegisterOperand DstRC, RegisterOperand SrcRC,
681 dag InOperandList = (ins SrcRC:$rt);
684 list<dag> Pattern = [(set DstRC:$fs, (OpNode SrcRC:$rt))];
690 string opstr, RegisterOperand DstRC, RegisterOperand SrcRC,
692 dag InOperandList = (ins DstRC:$fs_in, SrcRC:$rt);
704 RegisterOperand SrcRC> {
705 dag InOperandList = (ins SrcRC:$rt);
725 RegisterOperand SrcRC> {
[all …]
|
| D | MipsInstrFPU.td | 121 class ABSS_FT<string opstr, RegisterOperand DstRC, RegisterOperand SrcRC,
123 InstSE<(outs DstRC:$fd), (ins SrcRC:$fs), !strconcat(opstr, "\t$fd, $fs"),
124 [(set DstRC:$fd, (OpNode SrcRC:$fs))], Itin, FrmFR, opstr>,
144 class MFC1_FT<string opstr, RegisterOperand DstRC, RegisterOperand SrcRC,
146 InstSE<(outs DstRC:$rt), (ins SrcRC:$fs), !strconcat(opstr, "\t$rt, $fs"),
147 [(set DstRC:$rt, (OpNode SrcRC:$fs))], Itin, FrmFR, opstr>, HARDFLOAT;
149 class MTC1_FT<string opstr, RegisterOperand DstRC, RegisterOperand SrcRC,
151 InstSE<(outs DstRC:$fs), (ins SrcRC:$rt), !strconcat(opstr, "\t$rt, $fs"),
152 [(set DstRC:$fs, (OpNode SrcRC:$rt))], Itin, FrmFR, opstr>, HARDFLOAT;
154 class MTC1_64_FT<string opstr, RegisterOperand DstRC, RegisterOperand SrcRC,
[all …]
|
| /external/llvm/lib/Target/PowerPC/ |
| D | PPCVSXCopy.cpp | 106 const TargetRegisterClass *SrcRC = in processBlock() local
115 unsigned NewVReg = MRI.createVirtualRegister(SrcRC); in processBlock()
|
| /external/swiftshader/third_party/LLVM/lib/CodeGen/ |
| D | RegisterCoalescer.cpp | 156 const TargetRegisterClass *SrcRC,
289 const TargetRegisterClass *SrcRC = MRI.getRegClass(Src); in setRegisters() local
291 if (!TRI.getCommonSubClass(DstRC, SrcRC)) in setRegisters()
306 const TargetRegisterClass *SrcRC = MRI.getRegClass(Src); in setRegisters() local
309 NewRC = TRI.getMatchingSuperRegClass(DstRC, SrcRC, DstSub); in setRegisters()
311 NewRC = TRI.getCommonSubClass(DstRC, SrcRC); in setRegisters()
314 CrossClass = NewRC != DstRC || NewRC != SrcRC; in setRegisters()
1103 const TargetRegisterClass *SrcRC, in isWinToJoinCrossClass() argument
1135 if (SrcRC != NewRC && SrcSize > ThresSize) { in isWinToJoinCrossClass()
1136 unsigned SrcRCCount = RegClassInfo.getNumAllocatableRegs(SrcRC); in isWinToJoinCrossClass()
|
| /external/swiftshader/third_party/LLVM/lib/Target/X86/ |
| D | X86InstrMMX.td | 104 multiclass sse12_cvt_pint<bits<8> opc, RegisterClass SrcRC, RegisterClass DstRC,
107 def irr : PI<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src), asm,
108 [(set DstRC:$dst, (Int SrcRC:$src))], d>;
113 multiclass sse12_cvt_pint_3addr<bits<8> opc, RegisterClass SrcRC,
116 def irr : PI<opc, MRMSrcReg, (outs DstRC:$dst),(ins DstRC:$src1, SrcRC:$src2),
117 asm, [(set DstRC:$dst, (Int DstRC:$src1, SrcRC:$src2))], d>;
|
| /external/llvm/lib/Target/X86/ |
| D | X86InstrMMX.td | 185 multiclass sse12_cvt_pint<bits<8> opc, RegisterClass SrcRC, RegisterClass DstRC,
188 def irr : MMXPI<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src), asm,
189 [(set DstRC:$dst, (Int SrcRC:$src))], itins.rr, d>,
196 multiclass sse12_cvt_pint_3addr<bits<8> opc, RegisterClass SrcRC,
200 (ins DstRC:$src1, SrcRC:$src2), asm,
201 [(set DstRC:$dst, (Int DstRC:$src1, SrcRC:$src2))],
|
| /external/swiftshader/third_party/LLVM/lib/Target/PTX/ |
| D | PTXInstrInfo.h | 49 const TargetRegisterClass *SrcRC,
|
| D | PTXInstrInfo.cpp | 73 const TargetRegisterClass *SrcRC, in copyRegToReg() argument
75 if (DstRC != SrcRC) in copyRegToReg()
|
| /external/swiftshader/third_party/LLVM/lib/CodeGen/SelectionDAG/ |
| D | ScheduleDAGFast.cpp | 382 const TargetRegisterClass *SrcRC, in InsertCopiesAndMoveSuccs() argument
385 CopyFromSU->CopySrcRC = SrcRC; in InsertCopiesAndMoveSuccs()
390 CopyToSU->CopyDstRC = SrcRC; in InsertCopiesAndMoveSuccs()
|
| D | InstrEmitter.cpp | 137 const TargetRegisterClass *SrcRC = 0, *DstRC = 0; in EmitCopyFromReg() local
138 SrcRC = TRI->getMinimalPhysRegClass(SrcReg, VT); in EmitCopyFromReg()
152 if (MatchReg && SrcRC->getCopyCost() < 0) { in EmitCopyFromReg()
|
| /external/llvm/include/llvm/Target/ |
| D | TargetRegisterInfo.h | 519 const TargetRegisterClass *SrcRC,
920 const TargetRegisterClass *SrcRC, in shouldCoalesce() argument
|
| /external/llvm/lib/Target/ARM/ |
| D | ARMBaseRegisterInfo.h | 191 const TargetRegisterClass *SrcRC,
|
| D | ARMBaseRegisterInfo.cpp | 784 const TargetRegisterClass *SrcRC, in shouldCoalesce() argument
797 if (NewRC->getSize() < 32 && DstRC->getSize() < 32 && SrcRC->getSize() < 32) in shouldCoalesce()
803 MRI.getTargetRegisterInfo()->getRegClassWeight(SrcRC); in shouldCoalesce()
|
| /external/llvm/lib/CodeGen/SelectionDAG/ |
| D | ScheduleDAGFast.cpp | 389 const TargetRegisterClass *SrcRC, in InsertCopiesAndMoveSuccs() argument
392 CopyFromSU->CopySrcRC = SrcRC; in InsertCopiesAndMoveSuccs()
397 CopyToSU->CopyDstRC = SrcRC; in InsertCopiesAndMoveSuccs()
|
| D | InstrEmitter.cpp | 157 const TargetRegisterClass *SrcRC = nullptr, *DstRC = nullptr; in EmitCopyFromReg() local
158 SrcRC = TRI->getMinimalPhysRegClass(SrcReg, VT); in EmitCopyFromReg()
172 if (MatchReg && SrcRC->getCopyCost() < 0) { in EmitCopyFromReg()
|
| /external/llvm/lib/Target/Hexagon/ |
| D | HexagonGenInsert.cpp | 640 const TargetRegisterClass *SrcRC = MRI->getRegClass(SrcR); in isValidInsertForm() local
643 if (!isIntClass(DstRC) || !isIntClass(SrcRC) || !isIntClass(InsRC)) in isValidInsertForm()
646 if (DstRC != SrcRC) in isValidInsertForm()
|