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Searched refs:UseIdx (Results 1 – 25 of 44) sorted by relevance

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/external/llvm/include/llvm/MC/
DMCInstrItineraries.h187 unsigned UseClass, unsigned UseIdx) const { in hasPipelineForwarding() argument
197 if ((FirstUseIdx + UseIdx) >= LastUseIdx) in hasPipelineForwarding()
201 Forwardings[FirstUseIdx + UseIdx]; in hasPipelineForwarding()
208 unsigned UseClass, unsigned UseIdx) const { in getOperandLatency() argument
216 int UseCycle = getOperandCycle(UseClass, UseIdx); in getOperandLatency()
222 hasPipelineForwarding(DefClass, DefIdx, UseClass, UseIdx)) in getOperandLatency()
DMCSubtargetInfo.h136 int getReadAdvanceCycles(const MCSchedClassDesc *SC, unsigned UseIdx, in getReadAdvanceCycles() argument
143 if (I->UseIdx < UseIdx) in getReadAdvanceCycles()
145 if (I->UseIdx > UseIdx) in getReadAdvanceCycles()
DMCSchedule.h87 unsigned UseIdx; member
92 return UseIdx == Other.UseIdx && WriteResourceID == Other.WriteResourceID
/external/swiftshader/third_party/LLVM/include/llvm/MC/
DMCInstrItineraries.h200 unsigned UseClass, unsigned UseIdx) const { in hasPipelineForwarding() argument
210 if ((FirstUseIdx + UseIdx) >= LastUseIdx) in hasPipelineForwarding()
214 Forwardings[FirstUseIdx + UseIdx]; in hasPipelineForwarding()
221 unsigned UseClass, unsigned UseIdx) const { in getOperandLatency() argument
229 int UseCycle = getOperandCycle(UseClass, UseIdx); in getOperandLatency()
235 hasPipelineForwarding(DefClass, DefIdx, UseClass, UseIdx)) in getOperandLatency()
/external/swiftshader/third_party/LLVM/lib/Target/
DTargetInstrInfo.cpp67 const MachineInstr *UseMI, unsigned UseIdx) const { in getOperandLatency()
73 return ItinData->getOperandLatency(DefClass, DefIdx, UseClass, UseIdx); in getOperandLatency()
79 SDNode *UseNode, unsigned UseIdx) const { in getOperandLatency()
90 return ItinData->getOperandLatency(DefClass, DefIdx, UseClass, UseIdx); in getOperandLatency()
/external/swiftshader/third_party/LLVM/lib/CodeGen/
DLiveRangeEdit.cpp84 SlotIndex UseIdx, in allUsesAvailableAt() argument
87 UseIdx = UseIdx.getUseIndex(); in allUsesAvailableAt()
105 if (OVNI != li.getVNInfoAt(UseIdx)) in allUsesAvailableAt()
112 SlotIndex UseIdx, in canRematerializeAt() argument
136 if (!allUsesAvailableAt(RM.OrigMI, DefIdx, UseIdx, lis)) in canRematerializeAt()
DLiveRangeEdit.h82 SlotIndex UseIdx, LiveIntervals &lis);
159 SlotIndex UseIdx,
DInlineSpiller.cpp836 SlotIndex UseIdx = LIS.getInstructionIndex(MI).getUseIndex(); in reMaterializeFor() local
837 VNInfo *ParentVNI = VirtReg.getVNInfoAt(UseIdx.getBaseIndex()); in reMaterializeFor()
846 DEBUG(dbgs() << UseIdx << '\t' << *MI); in reMaterializeFor()
858 if (!Edit->canRematerializeAt(RM, UseIdx, false, LIS)) { in reMaterializeFor()
860 DEBUG(dbgs() << "\tcannot remat for " << UseIdx << '\t' << *MI); in reMaterializeFor()
874 DEBUG(dbgs() << "\tcannot remat tied reg: " << UseIdx << '\t' << *MI); in reMaterializeFor()
907 DEBUG(dbgs() << "\t " << UseIdx << '\t' << *MI); in reMaterializeFor()
910 NewLI.addRange(LiveRange(DefIdx, UseIdx.getDefIndex(), DefVNI)); in reMaterializeFor()
/external/swiftshader/third_party/LLVM/lib/Target/ARM/
DARMBaseInstrInfo.h210 const MachineInstr *UseMI, unsigned UseIdx) const;
214 SDNode *UseNode, unsigned UseIdx) const;
233 unsigned UseIdx, unsigned UseAlign) const;
237 unsigned UseIdx, unsigned UseAlign) const;
242 unsigned UseIdx, unsigned UseAlign) const;
253 const MachineInstr *UseMI, unsigned UseIdx) const;
DARMBaseInstrInfo.cpp2161 unsigned UseIdx, unsigned UseAlign) const { in getVSTMUseCycle() argument
2162 int RegNo = (int)(UseIdx+1) - UseMCID.getNumOperands() + 1; in getVSTMUseCycle()
2164 return ItinData->getOperandCycle(UseClass, UseIdx); in getVSTMUseCycle()
2201 unsigned UseIdx, unsigned UseAlign) const { in getSTMUseCycle() argument
2202 int RegNo = (int)(UseIdx+1) - UseMCID.getNumOperands() + 1; in getSTMUseCycle()
2204 return ItinData->getOperandCycle(UseClass, UseIdx); in getSTMUseCycle()
2231 unsigned UseIdx, unsigned UseAlign) const { in getOperandLatency() argument
2235 if (DefIdx < DefMCID.getNumDefs() && UseIdx < UseMCID.getNumOperands()) in getOperandLatency()
2236 return ItinData->getOperandLatency(DefClass, DefIdx, UseClass, UseIdx); in getOperandLatency()
2286 UseCycle = ItinData->getOperandCycle(UseClass, UseIdx); in getOperandLatency()
[all …]
/external/llvm/lib/CodeGen/
DTargetSchedule.cpp144 unsigned UseIdx = 0; in findUseIdx() local
148 ++UseIdx; in findUseIdx()
150 return UseIdx; in findUseIdx()
202 unsigned UseIdx = findUseIdx(UseMI, UseOperIdx); in computeOperandLatency() local
203 int Advance = STI->getReadAdvanceCycles(UseDesc, UseIdx, WriteID); in computeOperandLatency()
DLiveRangeEdit.cpp87 SlotIndex UseIdx) const { in allUsesAvailableAt()
89 UseIdx = UseIdx.getRegSlot(true); in allUsesAvailableAt()
110 if (SlotIndex::isSameInstr(OrigIdx, UseIdx)) in allUsesAvailableAt()
113 if (OVNI != li.getVNInfoAt(UseIdx)) in allUsesAvailableAt()
120 SlotIndex UseIdx, bool cheapAsAMove) { in canRematerializeAt() argument
137 if (!allUsesAvailableAt(RM.OrigMI, DefIdx, UseIdx)) in canRematerializeAt()
DLiveRangeCalc.cpp186 SlotIndex UseIdx; in extendToUses() local
191 UseIdx = Indexes->getMBBEndIdx(MI->getOperand(OpNo+1).getMBB()); in extendToUses()
203 UseIdx = Indexes->getInstructionIndex(*MI).getRegSlot(isEarlyClobber); in extendToUses()
208 extend(LR, UseIdx, Reg); in extendToUses()
DRegisterCoalescer.cpp213 void addUndefFlag(const LiveInterval &Int, SlotIndex UseIdx,
705 SlotIndex UseIdx = LIS->getInstructionIndex(*UseMI); in removeCopyByCommutingDef() local
706 LiveInterval::iterator US = IntA.FindSegmentContaining(UseIdx); in removeCopyByCommutingDef()
759 SlotIndex UseIdx = LIS->getInstructionIndex(*UseMI).getRegSlot(true); in removeCopyByCommutingDef() local
760 LiveInterval::iterator US = IntA.FindSegmentContaining(UseIdx); in removeCopyByCommutingDef()
780 SlotIndex DefIdx = UseIdx.getRegSlot(); in removeCopyByCommutingDef()
1193 SlotIndex UseIdx = LIS->getInstructionIndex(MI); in eliminateUndefCopy() local
1201 if (SR.liveAt(UseIdx)) { in eliminateUndefCopy()
1207 isLive = DstLI.liveAt(UseIdx); in eliminateUndefCopy()
1211 DEBUG(dbgs() << "\tnew undef: " << UseIdx << '\t' << MI); in eliminateUndefCopy()
[all …]
DMachineVerifier.cpp230 SlotIndex UseIdx, const LiveRange &LR, unsigned Reg,
1111 unsigned MONum, SlotIndex UseIdx, const LiveRange &LR, unsigned VRegOrUnit, in checkLivenessAtUse() argument
1113 LiveQueryResult LRQ = LR.Query(UseIdx); in checkLivenessAtUse()
1120 report_context(UseIdx); in checkLivenessAtUse()
1128 report_context(UseIdx); in checkLivenessAtUse()
1208 SlotIndex UseIdx = LiveInts->getInstructionIndex(*MI); in checkLiveness() local
1213 checkLivenessAtUse(MO, MONum, UseIdx, *LR, *Units); in checkLiveness()
1221 checkLivenessAtUse(MO, MONum, UseIdx, LI, Reg); in checkLiveness()
1232 checkLivenessAtUse(MO, MONum, UseIdx, SR, Reg, SR.LaneMask); in checkLiveness()
1233 LiveQueryResult LRQ = SR.Query(UseIdx); in checkLiveness()
[all …]
DInlineSpiller.cpp511 SlotIndex UseIdx = LIS.getInstructionIndex(MI).getRegSlot(true); in reMaterializeFor() local
512 VNInfo *ParentVNI = VirtReg.getVNInfoAt(UseIdx.getBaseIndex()); in reMaterializeFor()
521 DEBUG(dbgs() << UseIdx << '\t' << MI); in reMaterializeFor()
529 VNInfo *OrigVNI = OrigLI.getVNInfoAt(UseIdx); in reMaterializeFor()
533 if (!Edit->canRematerializeAt(RM, OrigVNI, UseIdx, false)) { in reMaterializeFor()
535 DEBUG(dbgs() << "\tcannot remat for " << UseIdx << '\t' << MI); in reMaterializeFor()
543 DEBUG(dbgs() << "\tcannot remat tied reg: " << UseIdx << '\t' << MI); in reMaterializeFor()
574 DEBUG(dbgs() << "\t " << UseIdx << '\t' << MI << '\n'); in reMaterializeFor()
/external/llvm/lib/Target/ARM/
DARMBaseInstrInfo.h284 unsigned UseIdx) const override;
287 SDNode *UseNode, unsigned UseIdx) const override;
317 unsigned UseIdx, unsigned UseAlign) const;
321 unsigned UseIdx, unsigned UseAlign) const;
326 unsigned UseIdx, unsigned UseAlign) const;
332 const MachineInstr &UseMI, unsigned UseIdx,
348 unsigned UseIdx) const override;
DARMBaseInstrInfo.cpp3263 unsigned UseIdx, unsigned UseAlign) const { in getVSTMUseCycle() argument
3264 int RegNo = (int)(UseIdx+1) - UseMCID.getNumOperands() + 1; in getVSTMUseCycle()
3266 return ItinData->getOperandCycle(UseClass, UseIdx); in getVSTMUseCycle()
3303 unsigned UseIdx, unsigned UseAlign) const { in getSTMUseCycle() argument
3304 int RegNo = (int)(UseIdx+1) - UseMCID.getNumOperands() + 1; in getSTMUseCycle()
3306 return ItinData->getOperandCycle(UseClass, UseIdx); in getSTMUseCycle()
3333 unsigned UseIdx, unsigned UseAlign) const { in getOperandLatency() argument
3337 if (DefIdx < DefMCID.getNumDefs() && UseIdx < UseMCID.getNumOperands()) in getOperandLatency()
3338 return ItinData->getOperandLatency(DefClass, DefIdx, UseClass, UseIdx); in getOperandLatency()
3388 UseCycle = ItinData->getOperandCycle(UseClass, UseIdx); in getOperandLatency()
[all …]
/external/llvm/lib/Target/PowerPC/
DPPCVSXSwapRemoval.cpp672 int UseIdx = SwapMap[&UseMI]; in recordUnoptimizableWebs() local
674 if (!SwapVector[UseIdx].IsSwap || SwapVector[UseIdx].IsLoad || in recordUnoptimizableWebs()
675 SwapVector[UseIdx].IsStore) { in recordUnoptimizableWebs()
683 DEBUG(dbgs() << " use " << UseIdx << ": "); in recordUnoptimizableWebs()
715 int UseIdx = SwapMap[&UseMI]; in recordUnoptimizableWebs() local
717 if (SwapVector[UseIdx].VSEMI->getOpcode() != MI->getOpcode()) { in recordUnoptimizableWebs()
725 DEBUG(dbgs() << " use " << UseIdx << ": "); in recordUnoptimizableWebs()
726 DEBUG(SwapVector[UseIdx].VSEMI->dump()); in recordUnoptimizableWebs()
756 int UseIdx = SwapMap[&UseMI]; in markSwapsForRemoval() local
757 SwapVector[UseIdx].WillRemove = 1; in markSwapsForRemoval()
DPPCInstrInfo.h121 unsigned UseIdx) const override;
124 SDNode *UseNode, unsigned UseIdx) const override { in getOperandLatency() argument
126 UseNode, UseIdx); in getOperandLatency()
DPPCInstrInfo.cpp144 unsigned UseIdx) const { in getOperandLatency()
146 UseMI, UseIdx); in getOperandLatency()
1235 unsigned UseIdx; in FoldImmediate() local
1236 for (UseIdx = 0; UseIdx < UseMI.getNumOperands(); ++UseIdx) in FoldImmediate()
1237 if (UseMI.getOperand(UseIdx).isReg() && in FoldImmediate()
1238 UseMI.getOperand(UseIdx).getReg() == Reg) in FoldImmediate()
1241 assert(UseIdx < UseMI.getNumOperands() && "Cannot find Reg in UseMI"); in FoldImmediate()
1242 assert(UseIdx < UseMCID.getNumOperands() && "No operand description for Reg"); in FoldImmediate()
1244 const MCOperandInfo *UseInfo = &UseMCID.OpInfo[UseIdx]; in FoldImmediate()
1273 UseMI.getOperand(UseIdx).setReg(ZeroReg); in FoldImmediate()
/external/llvm/include/llvm/CodeGen/
DLiveRangeEdit.h93 SlotIndex UseIdx) const;
204 bool canRematerializeAt(Remat &RM, VNInfo *OrigVNI, SlotIndex UseIdx,
/external/swiftshader/third_party/LLVM/include/llvm/Target/
DTargetInstrInfo.h645 const MachineInstr *UseMI, unsigned UseIdx) const;
649 SDNode *UseNode, unsigned UseIdx) const;
674 const MachineInstr *UseMI, unsigned UseIdx) const { in hasHighOperandLatency() argument
/external/llvm/include/llvm/Target/
DTargetInstrInfo.h1222 SDNode *UseNode, unsigned UseIdx) const;
1235 unsigned UseIdx) const;
1251 unsigned UseIdx) const;
1284 unsigned UseIdx) const { in hasHighOperandLatency() argument
/external/llvm/utils/TableGen/
DSubtargetEmitter.cpp959 for (unsigned UseIdx = 0, EndIdx = Reads.size(); in GenSchedClassTables() local
960 UseIdx != EndIdx; ++UseIdx) { in GenSchedClassTables()
962 FindReadAdvance(SchedModels.getSchedRead(Reads[UseIdx]), ProcModel); in GenSchedClassTables()
983 RAEntry.UseIdx = UseIdx; in GenSchedClassTables()
1095 OS << " {" << RAEntry.UseIdx << ", " in EmitSchedClassTables()

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