| /external/swiftshader/third_party/LLVM/lib/Target/PTX/ |
| D | PTXMachineFunctionInfo.h | 43 RegisterMap UsedRegs; variable
54 UsedRegs[PTX::RegPredRegisterClass] = RegisterList(); in PTXMachineFunctionInfo()
55 UsedRegs[PTX::RegI16RegisterClass] = RegisterList(); in PTXMachineFunctionInfo()
56 UsedRegs[PTX::RegI32RegisterClass] = RegisterList(); in PTXMachineFunctionInfo()
57 UsedRegs[PTX::RegI64RegisterClass] = RegisterList(); in PTXMachineFunctionInfo()
58 UsedRegs[PTX::RegF32RegisterClass] = RegisterList(); in PTXMachineFunctionInfo()
59 UsedRegs[PTX::RegF64RegisterClass] = RegisterList(); in PTXMachineFunctionInfo()
108 UsedRegs[TRC].push_back(Reg); in addVirtualRegister()
124 name += utostr(UsedRegs[TRC].size() - 1); in addVirtualRegister()
143 return UsedRegs.lookup(TRC).size(); in getNumRegistersForClass()
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| /external/llvm/lib/Target/AArch64/ |
| D | AArch64LoadStoreOptimizer.cpp | 99 BitVector ModifiedRegs, UsedRegs; member
1032 BitVector &UsedRegs, in trackRegDefsUses() argument
1049 UsedRegs.set(*AI); in trackRegDefsUses()
1114 UsedRegs.reset(); in findMatchingStore()
1141 trackRegDefsUses(MI, ModifiedRegs, UsedRegs, TRI); in findMatchingStore()
1225 UsedRegs.reset(); in findMatchingInsn()
1279 trackRegDefsUses(MI, ModifiedRegs, UsedRegs, TRI); in findMatchingInsn()
1289 trackRegDefsUses(MI, ModifiedRegs, UsedRegs, TRI); in findMatchingInsn()
1297 trackRegDefsUses(MI, ModifiedRegs, UsedRegs, TRI); in findMatchingInsn()
1306 trackRegDefsUses(MI, ModifiedRegs, UsedRegs, TRI); in findMatchingInsn()
[all …]
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| /external/llvm/lib/Target/X86/ |
| D | X86CallFrameOptimization.cpp | 101 DenseSet<unsigned int> &UsedRegs);
261 const X86RegisterInfo &RegInfo, DenseSet<unsigned int> &UsedRegs) { in classifyInstruction() argument
308 for (unsigned int U : UsedRegs) in classifyInstruction()
367 DenseSet<unsigned int> UsedRegs; in collectCallInfo() local
369 while ((Classification = classifyInstruction(MBB, I, RegInfo, UsedRegs)) != in collectCallInfo()
416 UsedRegs.insert(Reg); in collectCallInfo()
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| /external/llvm/lib/Target/AMDGPU/ |
| D | SIInsertWaits.cpp | 80 RegCounters UsedRegs; member in __anonbf0f7c4b0111::SIInsertWaits
351 UsedRegs[j] = Limit; in pushInstruction()
476 increaseCounters(Result, UsedRegs[j]); in handleOperands()
529 memset(&UsedRegs, 0, sizeof(UsedRegs)); in runOnMachineFunction()
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| /external/swiftshader/third_party/LLVM/lib/CodeGen/ |
| D | CallingConvLower.cpp | 36 UsedRegs.resize((TRI.getNumRegs()+31)/32); in CCState()
63 UsedRegs[Reg/32] |= 1 << (Reg&31); in MarkAllocated()
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| D | MachineInstr.cpp | 1692 void MachineInstr::setPhysRegsDeadExcept(const SmallVectorImpl<unsigned> &UsedRegs, in setPhysRegsDeadExcept() argument
1700 for (SmallVectorImpl<unsigned>::const_iterator I = UsedRegs.begin(), in setPhysRegsDeadExcept()
1701 E = UsedRegs.end(); I != E; ++I) in setPhysRegsDeadExcept()
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| /external/llvm/lib/Target/ARM/ |
| D | Thumb1FrameLowering.cpp | 467 LivePhysRegs UsedRegs(STI.getRegisterInfo()); in emitPopSpecialFixUp() local
468 UsedRegs.addLiveOuts(MBB); in emitPopSpecialFixUp()
476 UsedRegs.addReg(CSRegs[i]); in emitPopSpecialFixUp()
485 UsedRegs.stepBackward(*--InstUpToMBBI); in emitPopSpecialFixUp()
505 if (!UsedRegs.contains(Register)) { in emitPopSpecialFixUp()
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| D | ARMFastISel.cpp | 200 bool FinishCall(MVT RetVT, SmallVectorImpl<unsigned> &UsedRegs,
2016 bool ARMFastISel::FinishCall(MVT RetVT, SmallVectorImpl<unsigned> &UsedRegs, in FinishCall() argument
2043 UsedRegs.push_back(RVLocs[0].getLocReg()); in FinishCall()
2044 UsedRegs.push_back(RVLocs[1].getLocReg()); in FinishCall()
2062 UsedRegs.push_back(RVLocs[0].getLocReg()); in FinishCall()
2269 SmallVector<unsigned, 4> UsedRegs; in ARMEmitLibcall() local
2270 if (!FinishCall(RetVT, UsedRegs, I, CC, NumBytes, false)) return false; in ARMEmitLibcall()
2273 static_cast<MachineInstr *>(MIB)->setPhysRegsDeadExcept(UsedRegs, TRI); in ARMEmitLibcall()
2414 SmallVector<unsigned, 4> UsedRegs; in SelectCall() local
2415 if (!FinishCall(RetVT, UsedRegs, I, CC, NumBytes, isVarArg)) in SelectCall()
[all …]
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| D | ARMLoadStoreOptimizer.cpp | 821 DenseSet<unsigned> UsedRegs; in MergeOpsUpdate() local
830 UsedRegs.insert(Reg); in MergeOpsUpdate()
920 if (UsedRegs.count(MO.getReg())) in MergeOpsUpdate()
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| /external/llvm/lib/CodeGen/SelectionDAG/ |
| D | InstrEmitter.cpp | 833 SmallVector<unsigned, 8> UsedRegs; in EmitMachineNode() local
842 UsedRegs.push_back(Reg); in EmitMachineNode()
851 UsedRegs.push_back(cast<RegisterSDNode>(F->getOperand(1))->getReg()); in EmitMachineNode()
859 UsedRegs.append(MCID.getImplicitUses(), in EmitMachineNode()
867 UsedRegs.push_back(Reg); in EmitMachineNode()
873 if (!UsedRegs.empty() || II.getImplicitDefs()) in EmitMachineNode()
874 MIB->setPhysRegsDeadExcept(UsedRegs, *TRI); in EmitMachineNode()
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| /external/swiftshader/third_party/LLVM/include/llvm/CodeGen/ |
| D | CallingConvLower.h | 164 SmallVector<uint32_t, 16> UsedRegs; variable
191 return UsedRegs[Reg/32] & (1 << (Reg&31)); in isAllocated()
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| D | MachineInstr.h | 465 void setPhysRegsDeadExcept(const SmallVectorImpl<unsigned> &UsedRegs,
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| /external/llvm/lib/CodeGen/ |
| D | MachineBasicBlock.cpp | 766 SmallVector<unsigned, 4> UsedRegs; in SplitCriticalEdge() local
778 if (std::find(UsedRegs.begin(), UsedRegs.end(), Reg) == UsedRegs.end()) in SplitCriticalEdge()
779 UsedRegs.push_back(Reg); in SplitCriticalEdge()
919 LIS->repairIntervalsInRange(this, getFirstTerminator(), end(), UsedRegs); in SplitCriticalEdge()
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| D | CallingConvLower.cpp | 38 UsedRegs.resize((TRI.getNumRegs()+31)/32); in CCState()
64 UsedRegs[*AI/32] |= 1 << (*AI&31); in MarkAllocated()
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| D | MachineInstr.cpp | 2105 void MachineInstr::setPhysRegsDeadExcept(ArrayRef<unsigned> UsedRegs, in setPhysRegsDeadExcept() argument
2117 if (std::none_of(UsedRegs.begin(), UsedRegs.end(), in setPhysRegsDeadExcept()
2125 for (ArrayRef<unsigned>::iterator I = UsedRegs.begin(), E = UsedRegs.end(); in setPhysRegsDeadExcept()
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| /external/swiftshader/third_party/LLVM/lib/Target/ARM/ |
| D | ARMFastISel.cpp | 199 bool FinishCall(MVT RetVT, SmallVectorImpl<unsigned> &UsedRegs,
1668 bool ARMFastISel::FinishCall(MVT RetVT, SmallVectorImpl<unsigned> &UsedRegs, in FinishCall() argument
1695 UsedRegs.push_back(RVLocs[0].getLocReg()); in FinishCall()
1696 UsedRegs.push_back(RVLocs[1].getLocReg()); in FinishCall()
1708 UsedRegs.push_back(RVLocs[0].getLocReg()); in FinishCall()
1867 SmallVector<unsigned, 4> UsedRegs; in ARMEmitLibcall() local
1868 if (!FinishCall(RetVT, UsedRegs, I, CC, NumBytes)) return false; in ARMEmitLibcall()
1871 static_cast<MachineInstr *>(MIB)->setPhysRegsDeadExcept(UsedRegs, TRI); in ARMEmitLibcall()
1980 SmallVector<unsigned, 4> UsedRegs; in SelectCall() local
1981 if (!FinishCall(RetVT, UsedRegs, I, CC, NumBytes)) return false; in SelectCall()
[all …]
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| /external/swiftshader/third_party/LLVM/lib/CodeGen/SelectionDAG/ |
| D | InstrEmitter.cpp | 708 SmallVector<unsigned, 8> UsedRegs; in EmitMachineNode() local
711 UsedRegs.push_back(cast<RegisterSDNode>(F->getOperand(1))->getReg()); in EmitMachineNode()
715 UsedRegs.append(MCID.getImplicitUses(), in EmitMachineNode()
723 UsedRegs.push_back(Reg); in EmitMachineNode()
727 MI->setPhysRegsDeadExcept(UsedRegs, *TRI); in EmitMachineNode()
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| /external/llvm/include/llvm/CodeGen/ |
| D | CallingConvLower.h | 206 SmallVector<uint32_t, 16> UsedRegs; variable
291 return UsedRegs[Reg/32] & (1 << (Reg&31)); in isAllocated()
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| D | MachineInstr.h | 1113 void setPhysRegsDeadExcept(ArrayRef<unsigned> UsedRegs,
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| /external/swiftshader/third_party/LLVM/lib/Target/X86/ |
| D | X86FastISel.cpp | 1866 SmallVector<unsigned, 4> UsedRegs; in DoSelectCall() local
1890 UsedRegs.push_back(RVLocs[i].getLocReg()); in DoSelectCall()
1914 static_cast<MachineInstr *>(MIB)->setPhysRegsDeadExcept(UsedRegs, TRI); in DoSelectCall()
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