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Searched refs:VAL0 (Results 1 – 12 of 12) sorted by relevance

/external/llvm/test/CodeGen/AMDGPU/
Dds_write2.ll25 ; SI-DAG: buffer_load_dword [[VAL0:v[0-9]+]], {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, 0 add…
28 ; SI: ds_write2_b32 [[VPTR]], [[VAL0]], [[VAL1]] offset1:8
84 ; SI: buffer_load_dwordx2 v{{\[}}[[VAL0:[0-9]+]]:{{[0-9]+\]}}
87 ; SI: ds_write2_b32 [[VPTR]], v[[VAL0]], v[[VAL1]] offset1:8
106 ; SI-DAG: buffer_load_dwordx2 v{{\[}}[[VAL0:[0-9]+]]:[[VAL1:[0-9]+]]{{\]}}
108 ; SI: ds_write2_b32 [[VPTR]], v[[VAL0]], v[[VAL1]] offset1:8
125 ; SI-DAG: buffer_load_dwordx4 v{{\[}}[[VAL0:[0-9]+]]:[[VAL1:[0-9]+]]{{\]}}
127 ; SI: ds_write2_b32 [[VPTR]], v[[VAL0]], v[[VAL1]] offset1:8
144 ; SI-DAG: buffer_load_dword [[VAL0:v[0-9]+]], {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, 0 add…
147 ; SI: ds_write2_b32 [[VPTR]], [[VAL0]], [[VAL1]] offset1:255
[all …]
Dds_write2st64.ll23 ; SI-DAG: buffer_load_dword [[VAL0:v[0-9]+]], {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, 0 add…
26 ; SI: ds_write2st64_b32 [[VPTR]], [[VAL0]], [[VAL1]] offset0:2 offset1:5
44 ; SI-DAG: buffer_load_dword [[VAL0:v[0-9]+]], {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, 0 add…
47 ; SI: ds_write2st64_b32 [[VPTR]], [[VAL0]], [[VAL1]] offset1:255
64 ; SI-DAG: buffer_load_dwordx2 [[VAL0:v\[[0-9]+:[0-9]+\]]], {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9…
67 ; SI: ds_write2st64_b64 [[VPTR]], [[VAL0]], [[VAL1]] offset0:4 offset1:127
Dsminmax.ll154 ; GCN: s_load_dword [[VAL0:s[0-9]+]]
157 ; GCN-DAG: s_min_i32 s{{[0-9]+}}, [[VAL0]], [[VAL1]]
158 ; GCN-DAG: s_max_i32 s{{[0-9]+}}, [[VAL0]], [[VAL1]]
170 ; GCN: buffer_load_dword [[VAL0:v[0-9]+]]
173 ; GCN-DAG: v_min_i32_e32 v{{[0-9]+}}, [[VAL1]], [[VAL0]]
174 ; GCN-DAG: v_max_i32_e32 v{{[0-9]+}}, [[VAL1]], [[VAL0]]
Dctpop.ll42 ; GCN: buffer_load_dword [[VAL0:v[0-9]+]],
44 ; SI: v_bcnt_u32_b32_e32 [[RESULT:v[0-9]+]], [[VAL0]], [[MIDRESULT]]
45 ; VI: v_bcnt_u32_b32_e64 [[RESULT:v[0-9]+]], [[VAL0]], [[MIDRESULT]]
62 ; GCN: buffer_load_dword [[VAL0:v[0-9]+]],
64 ; GCN-NEXT: v_bcnt_u32_b32_e64 [[RESULT:v[0-9]+]], [[VAL0]], s{{[0-9]+}}
Dctpop64.ll173 ; GCN: buffer_load_dwordx4 v{{\[}}[[VAL0:[0-9]+]]:[[VAL3:[0-9]+]]{{\]}}, off, s{{\[[0-9]+:[0-9]+\]}…
178 ; GCN-DAG: v_bcnt_u32_b32_e64 [[MIDRESULT2:v[0-9]+]], v[[VAL0]], 0
Dshift-and-i128-ubfe.ll93 ; GCN: buffer_load_dwordx4 v{{\[}}[[VAL0:[0-9]+]]:[[VAL3:[0-9]+]]{{\]}}, v{{\[[0-9]+:[0-9]+\]}}, s{…
/external/syslinux/gpxe/src/drivers/net/
Damd8111e.c251 writel(VAL0 | APAD_XMT | REX_RTRY | REX_UFLO, mmio + CMD2); in amd8111e_start()
261 writel(VAL2 | RDMD0 | VAL0 | RUN, mmio + CMD0); in amd8111e_start()
367 writel(VAL3 | LCINTEN | VAL1 | TINTEN0 | VAL0 | RINTEN0, mmio + INTEN0); in amd8111e_enable_interrupt()
368 writel(VAL0 | INTREN, mmio + CMD0); in amd8111e_enable_interrupt()
376 writel(VAL0 | UINTCMD, mmio + CMD0); in amd8111e_force_interrupt()
Damd8111e.h193 VAL0 = (1 << 7), /* VAL bit for byte 0 */ enumerator
/external/llvm/test/CodeGen/AArch64/
Dsibling-call.ll76 ; CHECK: ldr [[VAL0:x[0-9]+]],
78 ; CHECK: str [[VAL0]],
/external/llvm/test/CodeGen/ARM/
Daggregate-padding.ll94 ; CHECK-DAG: ldrh [[VAL0:r[0-9]+]], [sp, #8]
96 ; CHECK: add r0, [[VAL0]], [[VAL2]]
/external/llvm/test/Transforms/DeadArgElim/
Daggregates.ll93 ; CHECK: [[VAL0:%.*]] = extractvalue [3 x i32] [i32 42, i32 43, i32 44], 0
94 ; CHECK: [[RESTMP:%.*]] = insertvalue [2 x i32] undef, i32 [[VAL0]], 0
/external/webp/src/dsp/
Ddec_neon.c311 #define STORE6_LANE(DST, VAL0, VAL1, LANE) do { \ argument
312 vst3_lane_u8((DST) - 3, (VAL0), (LANE)); \