/external/swiftshader/third_party/LLVM/test/CodeGen/ARM/ |
D | vfcmp.ll | 28 ; ole is implemented with VCGE 63 ; ugt is implemented with VCGE/VMVN 75 ; ult is implemented with VCGE/VMVN 114 ; uno is implemented with VCGT/VCGE/VORR/VMVN 128 ; ord is implemented with VCGT/VCGE/VORR
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D | vicmp.ll | 6 ; to VCGT and VCGE. Test all the operand types for not-equal but only sample
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/external/llvm/test/CodeGen/ARM/ |
D | vfcmp.ll | 28 ; ole is implemented with VCGE 63 ; ugt is implemented with VCGE/VMVN 75 ; ult is implemented with VCGE/VMVN 114 ; uno is implemented with VCGT/VCGE/VORR/VMVN 128 ; ord is implemented with VCGT/VCGE/VORR
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D | vicmp.ll | 6 ; to VCGT and VCGE. Test all the operand types for not-equal but only sample
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/external/vixl/test/aarch32/config/ |
D | cond-dt-drt-drd-drn-drm-float.json | 37 "Vcge", // VCGE{<c>}{<q>}.F32 {<Dd>}, <Dn>, <Dm> ; A2 38 // VCGE{<c>}{<q>}.F32 {<Dd>}, <Dn>, <Dm> ; T2
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/external/swiftshader/third_party/LLVM/lib/Target/ARM/ |
D | ARMISelLowering.h | 99 VCGE, // Vector compare greater than or equal. enumerator
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D | ARMISelLowering.cpp | 869 case ARMISD::VCGE: return "ARMISD::VCGE"; in getTargetNodeName() 3457 case ISD::SETGE: Opc = ARMISD::VCGE; break; in LowerVSETCC() 3461 case ISD::SETULT: Invert = true; Opc = ARMISD::VCGE; break; in LowerVSETCC() 3478 Op1 = DAG.getNode(ARMISD::VCGE, dl, VT, TmpOp0, TmpOp1); in LowerVSETCC() 3490 case ISD::SETGE: Opc = ARMISD::VCGE; break; in LowerVSETCC() 3528 if (Opc == ARMISD::VCGE) in LowerVSETCC() 3540 case ARMISD::VCGE: in LowerVSETCC()
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D | ARMInstrNEON.td | 52 def NEONvcge : SDNode<"ARMISD::VCGE", SDTARMVCMP>; 3673 // VCGE : Vector Compare Greater Than or Equal
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/external/arm-neon-tests/ |
D | ref-rvct-neon-nofp16.txt | 1373 VCGE/VCGEQ output: 1374 VCGE/VCGEQ:0:result_uint8x8 [] = { 0, 0, 0, 0, 0, 0, ff, ff, } 1375 VCGE/VCGEQ:1:result_uint16x4 [] = { 0, 0, ffff, ffff, } 1376 VCGE/VCGEQ:2:result_uint32x2 [] = { ffffffff, ffffffff, } 1377 VCGE/VCGEQ:3:result_uint8x8 [] = { 0, 0, 0, ff, ff, ff, ff, ff, } 1378 VCGE/VCGEQ:4:result_uint16x4 [] = { 0, 0, ffff, ffff, } 1379 VCGE/VCGEQ:5:result_uint32x2 [] = { 0, ffffffff, } 1380 VCGE/VCGEQ:6:result_uint8x16 [] = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ff, ff, ff, ff, } 1381 VCGE/VCGEQ:7:result_uint16x8 [] = { 0, 0, 0, 0, 0, 0, ffff, ffff, } 1382 VCGE/VCGEQ:8:result_uint32x4 [] = { 0, 0, ffffffff, ffffffff, } [all …]
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D | ref-rvct-neon.txt | 1465 VCGE/VCGEQ output: 1466 VCGE/VCGEQ:0:result_uint8x8 [] = { 0, 0, 0, 0, 0, 0, ff, ff, } 1467 VCGE/VCGEQ:1:result_uint16x4 [] = { 0, 0, ffff, ffff, } 1468 VCGE/VCGEQ:2:result_uint32x2 [] = { ffffffff, ffffffff, } 1469 VCGE/VCGEQ:3:result_uint8x8 [] = { 0, 0, 0, ff, ff, ff, ff, ff, } 1470 VCGE/VCGEQ:4:result_uint16x4 [] = { 0, 0, ffff, ffff, } 1471 VCGE/VCGEQ:5:result_uint32x2 [] = { 0, ffffffff, } 1472 VCGE/VCGEQ:6:result_uint8x16 [] = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ff, ff, ff, ff, } 1473 VCGE/VCGEQ:7:result_uint16x8 [] = { 0, 0, 0, 0, 0, 0, ffff, ffff, } 1474 VCGE/VCGEQ:8:result_uint32x4 [] = { 0, 0, ffffffff, ffffffff, } [all …]
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D | ref-rvct-all.txt | 1465 VCGE/VCGEQ output: 1466 VCGE/VCGEQ:0:result_uint8x8 [] = { 0, 0, 0, 0, 0, 0, ff, ff, } 1467 VCGE/VCGEQ:1:result_uint16x4 [] = { 0, 0, ffff, ffff, } 1468 VCGE/VCGEQ:2:result_uint32x2 [] = { ffffffff, ffffffff, } 1469 VCGE/VCGEQ:3:result_uint8x8 [] = { 0, 0, 0, ff, ff, ff, ff, ff, } 1470 VCGE/VCGEQ:4:result_uint16x4 [] = { 0, 0, ffff, ffff, } 1471 VCGE/VCGEQ:5:result_uint32x2 [] = { 0, ffffffff, } 1472 VCGE/VCGEQ:6:result_uint8x16 [] = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ff, ff, ff, ff, } 1473 VCGE/VCGEQ:7:result_uint16x8 [] = { 0, 0, 0, 0, 0, 0, ffff, ffff, } 1474 VCGE/VCGEQ:8:result_uint32x4 [] = { 0, 0, ffffffff, ffffffff, } [all …]
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D | expected_input4gcc-nofp16.txt | 1280 VCGE/VCGEQ output:
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D | expected_input4gcc.txt | 1372 VCGE/VCGEQ output:
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/external/llvm/lib/Target/ARM/ |
D | ARMISelLowering.h | 98 VCGE, // Vector compare greater than or equal. enumerator
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D | ARMScheduleSwift.td | 555 "VACLE", "VACLT", "VCEQ", "VCGE", "VCGT", "VCLE", "VCLT", "VRSHL",
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D | ARMISelLowering.cpp | 1173 case ARMISD::VCGE: return "ARMISD::VCGE"; in getTargetNodeName() 4904 case ISD::SETGE: Opc = ARMISD::VCGE; break; in LowerVSETCC() 4908 case ISD::SETULT: Invert = true; Opc = ARMISD::VCGE; break; in LowerVSETCC() 4925 Op1 = DAG.getNode(ARMISD::VCGE, dl, CmpVT, TmpOp0, TmpOp1); in LowerVSETCC() 4937 case ISD::SETGE: Opc = ARMISD::VCGE; break; in LowerVSETCC() 4975 if (Opc == ARMISD::VCGE) in LowerVSETCC() 4987 case ARMISD::VCGE: in LowerVSETCC()
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D | ARMScheduleA9.td | 2411 // VSBH/VRSBH/VHSUB/VQSUB/VABD/VCEQ/VCGE/VCGT/VMAX/VMIN/VPMAX/VPMIN/VABDL
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D | ARMInstrNEON.td | 497 def NEONvcge : SDNode<"ARMISD::VCGE", SDTARMVCMP>; 4729 // VCGE : Vector Compare Greater Than or Equal
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/external/v8/src/arm/ |
D | assembler-arm.cc | 4285 VCGE, enumerator 4322 case VCGE: in EncodeNeonBinOp() 4569 emit(EncodeNeonBinOp(VCGE, dt, dst, src1, src2)); in vcge()
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/external/clang/include/clang/Basic/ |
D | arm_neon.td | 552 def VCGE : SOpInst<"vcge", "udd", "csifUcUsUiQcQsQiQfQUcQUsQUi", OP_GE>;
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/external/valgrind/none/tests/arm/ |
D | neon128.stdout.exp | 387 ---- VCGE ---- 1844 ---- VCGE #0 ---- 3854 ---- VCGE (fp) ---- 4117 ---- VCGE (fp) #0 ----
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D | neon64.stdout.exp | 535 ---- VCGE ---- 3088 ---- VCGE #0 ---- 5788 ---- VCGE (fp) ---- 6247 ---- VCGE (fp) #0 ----
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