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Searched refs:VEC (Results 1 – 17 of 17) sorted by relevance

/external/llvm/test/Transforms/LoopVectorize/
Dif-pred-stores.ll3 …orize -enable-cond-stores-vec -verify-loop-info -simplifycfg < %s | FileCheck %s --check-prefix=VEC
4 …nd-stores-vec -verify-loop-info -simplifycfg -instcombine < %s | FileCheck %s --check-prefix=VEC-IC
14 ; VEC-LABEL: test
15 ; VEC: %[[v8:.+]] = icmp sgt <2 x i32> %{{.*}}, <i32 100, i32 100>
16 ; VEC: %[[v9:.+]] = add nsw <2 x i32> %{{.*}}, <i32 20, i32 20>
17 ; VEC: %[[v10:.+]] = and <2 x i1> %[[v8]], <i1 true, i1 true>
18 ; VEC: %[[v11:.+]] = extractelement <2 x i1> %[[v10]], i32 0
19 ; VEC: %[[v12:.+]] = icmp eq i1 %[[v11]], true
20 ; VEC: %[[v13:.+]] = extractelement <2 x i32> %[[v9]], i32 0
21 ; VEC: %[[v14:.+]] = extractelement <2 x i32*> %{{.*}}, i32 0
[all …]
Dinterleaved-accesses.ll792 ; CHECK: %[[VEC:.+]] = shufflevector <4 x i32> %[[SPLAT_Y]], <4 x i32> %[[SPLAT_Z]], <8 x i32> <i…
793 ; CHECK: store <8 x i32> %[[VEC]], {{.*}}
/external/llvm/test/Transforms/LoopVectorize/AArch64/
Darbitrary-induction-step.ll2 …-vectorize -force-vector-interleave=1 -force-vector-width=2 | FileCheck %s --check-prefix=FORCE-VEC
23 ; FORCE-VEC-LABEL: @ind_plus2(
24 ; FORCE-VEC: %wide.load = load <2 x i32>, <2 x i32>*
25 ; FORCE-VEC: mul nsw <2 x i32>
26 ; FORCE-VEC: add nsw <2 x i32>
27 ; FORCE-VEC: %index.next = add i64 %index, 2
28 ; FORCE-VEC: icmp eq i64 %index.next, 512
67 ; FORCE-VEC-LABEL: @ind_minus2(
68 ; FORCE-VEC: %wide.load = load <2 x i32>, <2 x i32>*
69 ; FORCE-VEC: mul nsw <2 x i32>
[all …]
/external/llvm/test/CodeGen/SystemZ/
Dvec-args-01.ll3 ; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z13 | FileCheck %s -check-prefix=CHECK-VEC
16 ; CHECK-VEC-LABEL: foo:
17 ; CHECK-VEC-DAG: vrepif %v24, 1
18 ; CHECK-VEC-DAG: vrepif %v26, 2
19 ; CHECK-VEC-DAG: vrepif %v28, 3
20 ; CHECK-VEC-DAG: vrepif %v30, 4
21 ; CHECK-VEC-DAG: vrepif %v25, 5
22 ; CHECK-VEC-DAG: vrepif %v27, 6
23 ; CHECK-VEC-DAG: vrepif %v29, 7
24 ; CHECK-VEC-DAG: vrepif %v31, 8
[all …]
Dvec-args-04.ll3 ; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z13 | FileCheck %s -check-prefix=CHECK-VEC
13 ; CHECK-VEC-LABEL: foo:
14 ; CHECK-VEC-DAG: vrepib %v24, 1
15 ; CHECK-VEC-DAG: vrepib %v26, 2
16 ; CHECK-VEC-DAG: vrepib %v28, 3
17 ; CHECK-VEC-DAG: vrepib %v30, 4
18 ; CHECK-VEC-DAG: vrepib %v25, 5
19 ; CHECK-VEC-DAG: vrepib %v27, 6
20 ; CHECK-VEC-DAG: vrepib %v29, 7
21 ; CHECK-VEC-DAG: vrepib %v31, 8
[all …]
Dvec-args-02.ll3 ; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z13 | FileCheck %s -check-prefix=CHECK-VEC
12 ; CHECK-VEC-LABEL: foo:
13 ; CHECK-VEC-DAG: vrepif %v24, 1
14 ; CHECK-VEC-DAG: vrepif %v26, 2
15 ; CHECK-VEC: brasl %r14, bar@PLT
Dvec-args-05.ll3 ; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z13 | FileCheck %s -check-prefix=CHECK-VEC
12 ; CHECK-VEC-LABEL: foo:
13 ; CHECK-VEC-DAG: vrepib %v24, 1
14 ; CHECK-VEC-DAG: vrepib %v26, 2
15 ; CHECK-VEC: brasl %r14, bar@PLT
/external/llvm/test/Transforms/InstCombine/
Dsincospi.ll1 …stcombine -S < %s -mtriple=x86_64-apple-macosx10.9 | FileCheck %s --check-prefix=CHECK-FLOAT-IN-VEC
26 ; CHECK-FLOAT-IN-VEC: [[VAL:%[a-z0-9]+]] = load float, float* @var32
27 ; CHECK-FLOAT-IN-VEC: [[SINCOS:%[a-z0-9]+]] = call <2 x float> @__sincospif_stret(float [[VAL]])
28 ; CHECK-FLOAT-IN-VEC: extractelement <2 x float> [[SINCOS]], i32 0
29 ; CHECK-FLOAT-IN-VEC: extractelement <2 x float> [[SINCOS]], i32 1
45 ; CHECK-FLOAT-IN-VEC: [[SINCOS:%[a-z0-9]+]] = call <2 x float> @__sincospif_stret(float 1.000000e+0…
46 ; CHECK-FLOAT-IN-VEC: extractelement <2 x float> [[SINCOS]], i32 0
47 ; CHECK-FLOAT-IN-VEC: extractelement <2 x float> [[SINCOS]], i32 1
63 ; CHECK-FLOAT-IN-VEC: [[VAL:%[a-z0-9]+]] = load double, double* @var64
64 ; CHECK-FLOAT-IN-VEC: [[SINCOS:%[a-z0-9]+]] = call { double, double } @__sincospi_stret(double [[VA…
[all …]
/external/mesa3d/src/gallium/drivers/nouveau/nv30/
Dnvfx_vertprog.c496 nvfx_vp_emit(vpc, arith(0, VEC, MOV, src[i].reg, NVFX_VP_MASK_ALL, in nvfx_vertprog_parse_instruction()
507 nvfx_vp_emit(vpc, arith(0, VEC, MOV, src[i].reg, NVFX_VP_MASK_ALL, in nvfx_vertprog_parse_instruction()
518 nvfx_vp_emit(vpc, arith(0, VEC, MOV, src[i].reg, NVFX_VP_MASK_ALL, in nvfx_vertprog_parse_instruction()
553 nvfx_vp_emit(vpc, arith(sat, VEC, ADD, dst, mask, src[0], none, src[1])); in nvfx_vertprog_parse_instruction()
556 nvfx_vp_emit(vpc, arith(0, VEC, ARL, dst, mask, src[0], none, none)); in nvfx_vertprog_parse_instruction()
560 nvfx_vp_emit(vpc, arith(0, VEC, FLR, tmp.reg, mask, neg(src[0]), none, none)); in nvfx_vertprog_parse_instruction()
561 nvfx_vp_emit(vpc, arith(sat, VEC, MOV, dst, mask, neg(tmp), none, none)); in nvfx_vertprog_parse_instruction()
564 insn = arith(0, VEC, MOV, none.reg, mask, src[0], none, none); in nvfx_vertprog_parse_instruction()
568 insn = arith(sat, VEC, MOV, dst, mask, src[2], none, none); in nvfx_vertprog_parse_instruction()
572 insn = arith(sat, VEC, MOV, dst, mask, src[1], none, none); in nvfx_vertprog_parse_instruction()
[all …]
/external/llvm/unittests/Transforms/Utils/
DASanStackFrameLayoutTest.cpp42 #define VEC(a) \ in TEST() macro
88 TestLayout(VEC(t), 8, 32, in TEST()
95 TestLayout(VEC(t), 8, 32, in TEST()
100 #undef VEC in TEST()
/external/antlr/antlr-3.4/runtime/CSharp3/Sources/Antlr3.Runtime.Test/Composition/
DVecMath_Parser.g39 VEC;
32 | OPEN_SQUARE expr ( COMMA expr )* CLOSE_SQUARE -> ^( VEC expr+ )
DSimplify.g320 : ^( MULT INT ^(VEC (e+=.)+) ) -> ^(VEC ^(MULT INT $e)+)
/external/valgrind/
DREADME.aarch64223 LDP,STP (immediate, simm7) (FP&VEC)
/external/llvm/test/CodeGen/Mips/msa/
Dvec.ll1 ; Test the MSA intrinsics that are encoded with the VEC instruction format.
/external/v8/src/s390/
Dconstants-s390.h535 V(vec, VEC, 0xE7DB) /* type = VRR_A VECTOR ELEMENT COMPARE */ \
/external/clang/lib/Frontend/Rewrite/
DRewriteModernObjC.cpp3875 #define SKIP_BITFIELDS(IX, ENDIX, VEC) { \ argument
3876 while ((IX < ENDIX) && VEC[IX]->isBitField()) \
/external/toolchain-utils/android_bench_suite/panorama_input/
Dtest_007.ppm6383 …}T��^��x��~����������������t��M�~J�~E��H��I��I��O��R��t��{���������������[VEC=-60 OK<JF7mh]����ʾ�…