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Searched refs:VGPR (Results 1 – 21 of 21) sorted by relevance

/external/llvm/include/llvm/IR/
DIntrinsicsAMDGPU.td191 [llvm_v4f32_ty], // vdata(VGPR)
192 [llvm_anyint_ty, // vaddr(VGPR)
206 [llvm_v4f32_ty, // vdata(VGPR)
207 llvm_anyint_ty, // vaddr(VGPR)
221 [llvm_i32_ty, // vdata(VGPR)
222 llvm_anyint_ty, // vaddr(VGPR)
243 [llvm_i32_ty, // src(VGPR)
244 llvm_i32_ty, // cmp(VGPR)
245 llvm_anyint_ty, // vaddr(VGPR)
255 llvm_i32_ty, // vindex(VGPR)
[all …]
/external/llvm/lib/Target/AMDGPU/
DSIIntrinsics.td25 llvm_anyint_ty, // vdata(VGPR), overloaded for types i32, v2i32, v4i32
27 llvm_i32_ty, // vaddr(VGPR)
41 [llvm_anyint_ty], // vdata(VGPR), overloaded for types i32, v2i32, v4i32
43 llvm_anyint_ty, // vaddr(VGPR)
57 [llvm_v4f32_ty], // vdata(VGPR)
58 [llvm_anyint_ty, // vaddr(VGPR)
73 [llvm_v4f32_ty], // vdata(VGPR)
74 [llvm_anyint_ty, // vaddr(VGPR)
DSIRegisterInfo.td107 // VGPR registers
109 def VGPR#Index : SIReg <"VGPR"#Index, Index> {
192 // VGPR 32-bit registers
194 (add (sequence "VGPR%u", 0, 255))> {
198 // VGPR 64-bit registers
203 // VGPR 96-bit registers
209 // VGPR 128-bit registers
216 // VGPR 256-bit registers
227 // VGPR 512-bit registers
378 // VSrc_* Operands with an SGPR, VGPR or a 32-bit immediate
[all …]
DSIMachineFunctionInfo.h124 unsigned VGPR; member
126 SpilledReg(unsigned R, int L) : VGPR (R), Lane (L) { } in SpilledReg()
127 SpilledReg() : VGPR(AMDGPU::NoRegister), Lane(-1) { } in SpilledReg()
129 bool hasReg() { return VGPR != AMDGPU::NoRegister;} in hasReg()
DSIMachineFunctionInfo.cpp222 Spill.VGPR = LaneVGPRs[LaneVGPRIdx]; in getSpilledReg()
DSIRegisterInfo.cpp534 Spill.VGPR) in eliminateFrameIndex()
599 .addReg(Spill.VGPR) in eliminateFrameIndex()
DSIInstrInfo.td114 SDTCisVT<1, iAny>, // vdata(VGPR)
116 SDTCisVT<3, i32>, // vaddr(VGPR)
DSIInstructions.td3055 // Offset in an 32-bit VGPR
/external/clang/test/SemaOpenCL/
Damdgpu-num-register-attrs.cl20 // Check 0 VGPR is accepted.
26 // Check both 0 SGPR and VGPR is accepted.
29 // Too large VGPR value.
/external/llvm/test/CodeGen/AMDGPU/
Dspill-scavenge-offset.ll8 ; When the offset of VGPR spills into scratch space gets too large, an additional SGPR
22 ; mark most VGPR registers as used to increase register pressure
Dadd_i64.ll20 ; Check that the SGPR add operand is correctly moved to a VGPR.
31 ; Swap the arguments. Check that the SGPR -> VGPR copy works with the
Dsgpr-copy-duplicate-operand.ll4 ; Copy VGPR -> SGPR used twice as an instruction operand, which is then
Dadd.ll141 ; %0 will be stored in a VGPR, so the comiler will be forced to copy %a
142 ; to a VGPR before doing the add.
Dsi-lod-bias.ll4 ; This shader has the potential to generated illegal VGPR to SGPR copies if
Dmadak.ll200 ; GCN: buffer_load_dword [[VGPR:v[0-9]+]]
202 ; GCN: v_mul_f32_e32 [[MUL:v[0-9]+]], [[VGPR]], [[MADAK]]
Dindirect-addressing-undef.mir2 # Getting an undef that is specifically a VGPR is tricky from IR
Dsalu-to-valu.ll20 ; Make sure we aren't using VGPR's for the srsrc operand of BUFFER_LOAD_*
Dand.ll63 ; Second use is a VGPR use of the constant.
Dlocal-atomics.ll31 ; XXX - Is it really necessary to load 4 into VGPR?
Dsgpr-copy.ll4 ; This test checks that no VGPR to SGPR copies are created by the register
/external/llvm/docs/
DLangRef.rst3466 - ``[0-9]v``: The 32-bit VGPR register, number 0-9.