Searched refs:VG_IS_4_ALIGNED (Results 1 – 9 of 9) sorted by relevance
107 CHECK( VG_IS_4_ALIGNED(0x0) ); in test_VG_IS_XYZ_ALIGNED()108 CHECK( ! VG_IS_4_ALIGNED(0x1) ); in test_VG_IS_XYZ_ALIGNED()109 CHECK( ! VG_IS_4_ALIGNED(0x2) ); in test_VG_IS_XYZ_ALIGNED()110 CHECK( ! VG_IS_4_ALIGNED(0x3) ); in test_VG_IS_XYZ_ALIGNED()111 CHECK( VG_IS_4_ALIGNED(0x4) ); in test_VG_IS_XYZ_ALIGNED()112 CHECK( ! VG_IS_4_ALIGNED(0x5) ); in test_VG_IS_XYZ_ALIGNED()113 CHECK( ! VG_IS_4_ALIGNED(0x6) ); in test_VG_IS_XYZ_ALIGNED()114 CHECK( ! VG_IS_4_ALIGNED(0x7) ); in test_VG_IS_XYZ_ALIGNED()115 CHECK( VG_IS_4_ALIGNED(0x8) ); in test_VG_IS_XYZ_ALIGNED()116 CHECK( ! VG_IS_4_ALIGNED(0x9) ); in test_VG_IS_XYZ_ALIGNED()[all …]
1397 && nBits == 32 && VG_IS_4_ALIGNED(a))) { in mc_LOADVn_slow()1498 && VG_IS_4_ALIGNED(a) && nBits == 32 && n_addrs_bad < 4) { in mc_LOADVn_slow()1561 && nBits == 32 && VG_IS_4_ALIGNED(a))) { in mc_STOREVn_slow()1961 aligned = VG_IS_4_ALIGNED(src) && VG_IS_4_ALIGNED(dst); in MC_()2846 if (VG_IS_4_ALIGNED( -VG_STACK_REDZONE_SZB + new_SP )) { in mc_new_mem_stack_4_w_ECU()2857 if (VG_IS_4_ALIGNED( -VG_STACK_REDZONE_SZB + new_SP )) { in mc_new_mem_stack_4()2868 if (VG_IS_4_ALIGNED( -VG_STACK_REDZONE_SZB + new_SP )) { in mc_die_mem_stack_4()2884 } else if (VG_IS_4_ALIGNED( -VG_STACK_REDZONE_SZB + new_SP )) { in mc_new_mem_stack_8_w_ECU()2898 } else if (VG_IS_4_ALIGNED( -VG_STACK_REDZONE_SZB + new_SP )) { in mc_new_mem_stack_8()2912 } else if (VG_IS_4_ALIGNED( -VG_STACK_REDZONE_SZB + new_SP )) { in mc_die_mem_stack_8()[all …]
681 if (VG_IS_4_ALIGNED(dI) && VG_IS_4_ALIGNED(sI)) { in VG_()751 while ((!VG_IS_4_ALIGNED(d)) && sz >= 1) { in VG_()
351 VG_IS_4_ALIGNED(uregs.xbp))
192 #define VG_IS_4_ALIGNED(aaa_p) (0 == (((Addr)(aaa_p)) & ((Addr)0x3))) macro
768 vg_assert(VG_IS_4_ALIGNED(offsetof(VexGuestX86State,guest_EAX))); in do_pre_run_checks()769 vg_assert(VG_IS_4_ALIGNED(offsetof(VexGuestX86State,guest_EIP))); in do_pre_run_checks()
3799 if (UNLIKELY( !VG_IS_4_ALIGNED(a) )) in Filter__ok_to_skip_crd32()3914 if (UNLIKELY( !VG_IS_4_ALIGNED(a) )) in Filter__ok_to_skip_cwr32()
2629 vg_assert(di && VG_IS_4_ALIGNED(di)); in find_DiCfSI()
6253 if (!VG_IS_4_ALIGNED(ehdr->e_phentsize)) {