/external/llvm/lib/Target/ARM/ |
D | ARMHazardRecognizer.cpp | 27 if (Opcode == ARM::VMOVRS || Opcode == ARM::VMOVRRD) in hasRAWHazard()
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D | MLxExpansionPass.cpp | 192 if (Opcode == ARM::VMOVRS || Opcode == ARM::VMOVRRD) in hasRAWHazard()
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D | ARMISelLowering.h | 76 VMOVRRD, // double to two gprs. enumerator
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D | ARMISelLowering.cpp | 1151 case ARMISD::VMOVRRD: return "ARMISD::VMOVRRD"; in getTargetNodeName() 1552 SDValue fmrrd = DAG.getNode(ARMISD::VMOVRRD, dl, in PassF64ArgInRegs() 2305 SDValue HalfGPRs = DAG.getNode(ARMISD::VMOVRRD, dl, in LowerReturn() 2327 SDValue fmrrd = DAG.getNode(ARMISD::VMOVRRD, dl, in LowerReturn() 2395 } else if (Copy->getOpcode() == ARMISD::VMOVRRD) { in isUsedByReturnOnly() 3701 FalseVal = DAG.getNode(ARMISD::VMOVRRD, dl, in getCMOV() 3703 TrueVal = DAG.getNode(ARMISD::VMOVRRD, dl, in getCMOV() 4300 Tmp1 = DAG.getNode(ARMISD::VMOVRRD, dl, DAG.getVTList(MVT::i32, MVT::i32), in LowerFCOPYSIGN() 4316 Tmp0 = DAG.getNode(ARMISD::VMOVRRD, dl, DAG.getVTList(MVT::i32, MVT::i32), in LowerFCOPYSIGN() 4487 Cvt = DAG.getNode(ARMISD::VMOVRRD, dl, in ExpandBITCAST() [all …]
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D | ARMISelDAGToDAG.cpp | 442 if (Opcode == ARM::VMOVRS || Opcode == ARM::VMOVRRD) in hasNoVMLxHazardUse() 2893 case ARMISD::VMOVRRD: in Select() 2894 ReplaceNode(N, CurDAG->getMachineNode(ARM::VMOVRRD, dl, MVT::i32, MVT::i32, in Select()
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D | ARMInstrVFP.td | 1032 def VMOVRRD : AVConv3I<0b11000101, 0b1011, 2290 (VMOVRRD GPR:$Rt, GPR:$Rt2, DPR:$Dn, pred:$p)>;
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D | ARMFastISel.cpp | 1990 TII.get(ARM::VMOVRRD), VA.getLocReg()) in ProcessCallArgs()
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D | ARMBaseInstrInfo.cpp | 4627 case ARM::VMOVRRD: in getExtractSubregLikeInputs()
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/external/swiftshader/third_party/LLVM/lib/Target/ARM/ |
D | ARMHazardRecognizer.cpp | 27 if (Opcode == ARM::VMOVRS || Opcode == ARM::VMOVRRD) in hasRAWHazard()
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D | MLxExpansionPass.cpp | 145 if (Opcode == ARM::VMOVRS || Opcode == ARM::VMOVRRD) in hasRAWHazard()
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D | ARMISelLowering.h | 79 VMOVRRD, // double to two gprs. enumerator
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D | ARMISelLowering.cpp | 849 case ARMISD::VMOVRRD: return "ARMISD::VMOVRRD"; in getTargetNodeName() 1195 SDValue fmrrd = DAG.getNode(ARMISD::VMOVRRD, dl, in PassF64ArgInRegs() 1814 SDValue HalfGPRs = DAG.getNode(ARMISD::VMOVRRD, dl, in LowerReturn() 1831 SDValue fmrrd = DAG.getNode(ARMISD::VMOVRRD, dl, in LowerReturn() 1866 } else if (Use->getOpcode() == ARMISD::VMOVRRD) { in isUsedByReturnOnly() 3142 Tmp1 = DAG.getNode(ARMISD::VMOVRRD, dl, DAG.getVTList(MVT::i32, MVT::i32), in LowerFCOPYSIGN() 3158 Tmp0 = DAG.getNode(ARMISD::VMOVRRD, dl, DAG.getVTList(MVT::i32, MVT::i32), in LowerFCOPYSIGN() 3233 SDValue Cvt = DAG.getNode(ARMISD::VMOVRRD, dl, in ExpandBITCAST() 6958 if (Op0.getOpcode() == ARMISD::VMOVRRD && in PerformVMOVDRRCombine() 7936 case ARMISD::VMOVRRD: return PerformVMOVRRDCombine(N, DCI); in PerformDAGCombine()
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D | ARMISelDAGToDAG.cpp | 358 if (Opcode == ARM::VMOVRS || Opcode == ARM::VMOVRRD) in hasNoVMLxHazardUse() 2555 case ARMISD::VMOVRRD: in Select() 2556 return CurDAG->getMachineNode(ARM::VMOVRRD, dl, MVT::i32, MVT::i32, in Select()
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D | ARMFastISel.cpp | 1649 TII.get(ARM::VMOVRRD), VA.getLocReg()) in ProcessCallArgs()
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D | ARMInstrVFP.td | 507 def VMOVRRD : AVConv3I<0b11000101, 0b1011,
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/external/swiftshader/third_party/LLVM/test/CodeGen/ARM/ |
D | vector-DAGCombine.ll | 30 ; Radar 8407927: Make sure that VMOVRRD gets optimized away when the result is
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/external/llvm/test/CodeGen/ARM/ |
D | vector-DAGCombine.ll | 38 ; Radar 8407927: Make sure that VMOVRRD gets optimized away when the result is
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/external/capstone/arch/ARM/ |
D | ARMGenAsmWriter.inc | 1374 27378U, // VMOVRRD 4167 0U, // VMOVRRD 9874 // (VMOVRRD GPR:$Rt, GPR:$Rt2, DPR:$Dn, pred:$p)
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D | ARMGenInstrInfo.inc | 4551 …CID_Predicable), 0x18980ULL, nullptr, nullptr, OperandInfo204,0,nullptr }, // Inst #1357 = VMOVRRD
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D | ARMGenDisassemblerTables.inc | 8912 /* 444 */ MCD_OPC_Decode, 205, 10, 196, 2, // Opcode: VMOVRRD
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