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Searched refs:VMOVRRD (Results 1 – 20 of 20) sorted by relevance

/external/llvm/lib/Target/ARM/
DARMHazardRecognizer.cpp27 if (Opcode == ARM::VMOVRS || Opcode == ARM::VMOVRRD) in hasRAWHazard()
DMLxExpansionPass.cpp192 if (Opcode == ARM::VMOVRS || Opcode == ARM::VMOVRRD) in hasRAWHazard()
DARMISelLowering.h76 VMOVRRD, // double to two gprs. enumerator
DARMISelLowering.cpp1151 case ARMISD::VMOVRRD: return "ARMISD::VMOVRRD"; in getTargetNodeName()
1552 SDValue fmrrd = DAG.getNode(ARMISD::VMOVRRD, dl, in PassF64ArgInRegs()
2305 SDValue HalfGPRs = DAG.getNode(ARMISD::VMOVRRD, dl, in LowerReturn()
2327 SDValue fmrrd = DAG.getNode(ARMISD::VMOVRRD, dl, in LowerReturn()
2395 } else if (Copy->getOpcode() == ARMISD::VMOVRRD) { in isUsedByReturnOnly()
3701 FalseVal = DAG.getNode(ARMISD::VMOVRRD, dl, in getCMOV()
3703 TrueVal = DAG.getNode(ARMISD::VMOVRRD, dl, in getCMOV()
4300 Tmp1 = DAG.getNode(ARMISD::VMOVRRD, dl, DAG.getVTList(MVT::i32, MVT::i32), in LowerFCOPYSIGN()
4316 Tmp0 = DAG.getNode(ARMISD::VMOVRRD, dl, DAG.getVTList(MVT::i32, MVT::i32), in LowerFCOPYSIGN()
4487 Cvt = DAG.getNode(ARMISD::VMOVRRD, dl, in ExpandBITCAST()
[all …]
DARMISelDAGToDAG.cpp442 if (Opcode == ARM::VMOVRS || Opcode == ARM::VMOVRRD) in hasNoVMLxHazardUse()
2893 case ARMISD::VMOVRRD: in Select()
2894 ReplaceNode(N, CurDAG->getMachineNode(ARM::VMOVRRD, dl, MVT::i32, MVT::i32, in Select()
DARMInstrVFP.td1032 def VMOVRRD : AVConv3I<0b11000101, 0b1011,
2290 (VMOVRRD GPR:$Rt, GPR:$Rt2, DPR:$Dn, pred:$p)>;
DARMFastISel.cpp1990 TII.get(ARM::VMOVRRD), VA.getLocReg()) in ProcessCallArgs()
DARMBaseInstrInfo.cpp4627 case ARM::VMOVRRD: in getExtractSubregLikeInputs()
/external/swiftshader/third_party/LLVM/lib/Target/ARM/
DARMHazardRecognizer.cpp27 if (Opcode == ARM::VMOVRS || Opcode == ARM::VMOVRRD) in hasRAWHazard()
DMLxExpansionPass.cpp145 if (Opcode == ARM::VMOVRS || Opcode == ARM::VMOVRRD) in hasRAWHazard()
DARMISelLowering.h79 VMOVRRD, // double to two gprs. enumerator
DARMISelLowering.cpp849 case ARMISD::VMOVRRD: return "ARMISD::VMOVRRD"; in getTargetNodeName()
1195 SDValue fmrrd = DAG.getNode(ARMISD::VMOVRRD, dl, in PassF64ArgInRegs()
1814 SDValue HalfGPRs = DAG.getNode(ARMISD::VMOVRRD, dl, in LowerReturn()
1831 SDValue fmrrd = DAG.getNode(ARMISD::VMOVRRD, dl, in LowerReturn()
1866 } else if (Use->getOpcode() == ARMISD::VMOVRRD) { in isUsedByReturnOnly()
3142 Tmp1 = DAG.getNode(ARMISD::VMOVRRD, dl, DAG.getVTList(MVT::i32, MVT::i32), in LowerFCOPYSIGN()
3158 Tmp0 = DAG.getNode(ARMISD::VMOVRRD, dl, DAG.getVTList(MVT::i32, MVT::i32), in LowerFCOPYSIGN()
3233 SDValue Cvt = DAG.getNode(ARMISD::VMOVRRD, dl, in ExpandBITCAST()
6958 if (Op0.getOpcode() == ARMISD::VMOVRRD && in PerformVMOVDRRCombine()
7936 case ARMISD::VMOVRRD: return PerformVMOVRRDCombine(N, DCI); in PerformDAGCombine()
DARMISelDAGToDAG.cpp358 if (Opcode == ARM::VMOVRS || Opcode == ARM::VMOVRRD) in hasNoVMLxHazardUse()
2555 case ARMISD::VMOVRRD: in Select()
2556 return CurDAG->getMachineNode(ARM::VMOVRRD, dl, MVT::i32, MVT::i32, in Select()
DARMFastISel.cpp1649 TII.get(ARM::VMOVRRD), VA.getLocReg()) in ProcessCallArgs()
DARMInstrVFP.td507 def VMOVRRD : AVConv3I<0b11000101, 0b1011,
/external/swiftshader/third_party/LLVM/test/CodeGen/ARM/
Dvector-DAGCombine.ll30 ; Radar 8407927: Make sure that VMOVRRD gets optimized away when the result is
/external/llvm/test/CodeGen/ARM/
Dvector-DAGCombine.ll38 ; Radar 8407927: Make sure that VMOVRRD gets optimized away when the result is
/external/capstone/arch/ARM/
DARMGenAsmWriter.inc1374 27378U, // VMOVRRD
4167 0U, // VMOVRRD
9874 // (VMOVRRD GPR:$Rt, GPR:$Rt2, DPR:$Dn, pred:$p)
DARMGenInstrInfo.inc4551 …CID_Predicable), 0x18980ULL, nullptr, nullptr, OperandInfo204,0,nullptr }, // Inst #1357 = VMOVRRD
DARMGenDisassemblerTables.inc8912 /* 444 */ MCD_OPC_Decode, 205, 10, 196, 2, // Opcode: VMOVRRD