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Searched refs:VMUL (Results 1 – 21 of 21) sorted by relevance

/external/llvm/test/CodeGen/ARM/
Dneon-spfp.ll19 ; This test makes sure we're not lowering VMUL.f32 D* (aka. NEON) for single-prec. FP ops, since
/external/arm-neon-tests/
Dref-rvct-neon-nofp16.txt4597 VMUL output:
4598 VMUL:0:result_int8x8 [] = { fffffff0, 1, 12, 23, 34, 45, 56, 67, }
4599 VMUL:1:result_int16x4 [] = { fffffde0, fffffe02, fffffe24, fffffe46, }
4600 VMUL:2:result_int32x2 [] = { fffffcd0, fffffd03, }
4601 VMUL:3:result_int64x1 [] = { 3333333333333333, }
4602 VMUL:4:result_uint8x8 [] = { c0, 4, 48, 8c, d0, 14, 58, 9c, }
4603 VMUL:5:result_uint16x4 [] = { fab0, fb05, fb5a, fbaf, }
4604 VMUL:6:result_uint32x2 [] = { fffff9a0, fffffa06, }
4605 VMUL:7:result_uint64x1 [] = { 3333333333333333, }
4606 VMUL:8:result_poly8x8 [] = { c0, 84, 48, c, d0, 94, 58, 1c, }
[all …]
Dref-rvct-neon.txt5395 VMUL output:
5396 VMUL:0:result_int8x8 [] = { fffffff0, 1, 12, 23, 34, 45, 56, 67, }
5397 VMUL:1:result_int16x4 [] = { fffffde0, fffffe02, fffffe24, fffffe46, }
5398 VMUL:2:result_int32x2 [] = { fffffcd0, fffffd03, }
5399 VMUL:3:result_int64x1 [] = { 3333333333333333, }
5400 VMUL:4:result_uint8x8 [] = { c0, 4, 48, 8c, d0, 14, 58, 9c, }
5401 VMUL:5:result_uint16x4 [] = { fab0, fb05, fb5a, fbaf, }
5402 VMUL:6:result_uint32x2 [] = { fffff9a0, fffffa06, }
5403 VMUL:7:result_uint64x1 [] = { 3333333333333333, }
5404 VMUL:8:result_poly8x8 [] = { c0, 84, 48, c, d0, 94, 58, 1c, }
[all …]
Dref-rvct-all.txt5395 VMUL output:
5396 VMUL:0:result_int8x8 [] = { fffffff0, 1, 12, 23, 34, 45, 56, 67, }
5397 VMUL:1:result_int16x4 [] = { fffffde0, fffffe02, fffffe24, fffffe46, }
5398 VMUL:2:result_int32x2 [] = { fffffcd0, fffffd03, }
5399 VMUL:3:result_int64x1 [] = { 3333333333333333, }
5400 VMUL:4:result_uint8x8 [] = { c0, 4, 48, 8c, d0, 14, 58, 9c, }
5401 VMUL:5:result_uint16x4 [] = { fab0, fb05, fb5a, fbaf, }
5402 VMUL:6:result_uint32x2 [] = { fffff9a0, fffffa06, }
5403 VMUL:7:result_uint64x1 [] = { 3333333333333333, }
5404 VMUL:8:result_poly8x8 [] = { c0, 84, 48, c, d0, 94, 58, 1c, }
[all …]
Dexpected_input4gcc-nofp16.txt4838 VMUL output:
Dexpected_input4gcc.txt5204 VMUL output:
/external/swiftshader/third_party/LLVM/lib/Target/ARM/
DARMScheduleA8.td778 // Double-register FP VMUL
789 // Quad-register FP VMUL
DARMScheduleA9.td1649 // Double-register FP VMUL
1671 // Quad-register FP VMUL
DARMInstrNEON.td3410 // VMUL : Vector Multiply (integer, polynomial and floating-point)
3411 defm VMUL : N3V_QHS<0, 0, 0b1001, 1, IIC_VMULi16D, IIC_VMULi32D,
/external/llvm/lib/Target/ARM/
DARMScheduleA8.td793 // Double-register FP VMUL
804 // Quad-register FP VMUL
DARMScheduleSwift.td598 (instregex "VMUL(S|v|p|f|s)", "VNMULS", "VQDMULH", "VQRDMULH",
DARMScheduleA9.td1678 // Double-register FP VMUL
1700 // Quad-register FP VMUL
DARMInstrNEON.td4172 // VMUL : Vector Multiply (integer, polynomial and floating-point)
4173 defm VMUL : N3V_QHS<0, 0, 0b1001, 1, IIC_VMULi16D, IIC_VMULi32D,
/external/v8/src/arm/
Dassembler-arm.cc4280 VMUL, enumerator
4307 case VMUL: in EncodeNeonBinOp()
4414 emit(EncodeNeonBinOp(VMUL, size, dst, src1, src2)); in vmul()
/external/clang/include/clang/Basic/
Darm_neon.td519 def VMUL : IOpInst<"vmul", "ddd", "csifUcUsUiQcQsQiQfQUcQUsQUi", OP_MUL>;
/external/valgrind/none/tests/arm/
Dvfp.stdout.exp313 ---- VMUL (fp) ----
Dneon128.stdout.exp1394 ---- VMUL ----
1411 ---- VMUL (by scalar) ----
3068 ---- VMUL (fp) ----
3109 ---- VMUL (fp by scalar) ----
Dneon64.stdout.exp1671 ---- VMUL ----
1704 ---- VMUL (by scalar) ----
4462 ---- VMUL (fp) ----
4543 ---- VMUL (fp by scalar) ----
/external/swiftshader/third_party/LLVM/lib/Target/X86/
DX86InstrSSE.td2753 defm VMUL : basic_sse12_fp_binop_s<0x59, "mul", fmul, 0>,
2755 defm VMUL : basic_sse12_fp_binop_p<0x59, "mul", fmul, 0>,
/external/llvm/lib/Target/X86/
DX86InstrAVX512.td3827 defm VMUL : avx512_binop_s_round<0x59, "vmul", fmul, X86fmulRnd, SSE_ALU_ITINS_S, 1>;
3948 defm VMUL : avx512_fp_binop_p<0x59, "vmul", fmul, HasAVX512, 1>,
/external/valgrind/
DNEWS2338 277663 ARM: NEON float VMUL by scalar incorrect