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Searched refs:VREV32 (Results 1 – 14 of 14) sorted by relevance

/external/swiftshader/third_party/LLVM/lib/Target/ARM/
DARMISelLowering.h156 VREV32, // reverse elements within 32-bit words enumerator
DARMISelLowering.cpp906 case ARMISD::VREV32: return "ARMISD::VREV32"; in getTargetNodeName()
4273 return DAG.getNode(ARMISD::VREV32, dl, VT, OpLHS); in GeneratePerfectShuffle()
4369 return DAG.getNode(ARMISD::VREV32, dl, VT, V1); in LowerVECTOR_SHUFFLE()
DARMInstrNEON.td132 def NEONvrev32 : SDNode<"ARMISD::VREV32", SDTARMVSHUF>;
4706 // VREV32 : Vector Reverse elements within 32-bit words
/external/swiftshader/third_party/LLVM/test/CodeGen/ARM/
Dvrev.ll151 ; vrev <4 x i16> should use VREV32 and not VREV64
/external/arm-neon-tests/
Dref-rvct-neon-nofp16.txt2975 VREV32 output:
2976 VREV32:22:result_int8x8 [] = { fffffff3, fffffff2, fffffff1, fffffff0, fffffff7, fffffff6, fffffff5…
2977 VREV32:23:result_int16x4 [] = { fffffff1, fffffff0, fffffff3, fffffff2, }
2978 VREV32:24:result_int32x2 [] = { 33333333, 33333333, }
2979 VREV32:25:result_int64x1 [] = { 3333333333333333, }
2980 VREV32:26:result_uint8x8 [] = { f3, f2, f1, f0, f7, f6, f5, f4, }
2981 VREV32:27:result_uint16x4 [] = { fff1, fff0, fff3, fff2, }
2982 VREV32:28:result_uint32x2 [] = { 33333333, 33333333, }
2983 VREV32:29:result_uint64x1 [] = { 3333333333333333, }
2984 VREV32:30:result_poly8x8 [] = { f3, f2, f1, f0, f7, f6, f5, f4, }
[all …]
Dref-rvct-neon.txt3397 VREV32 output:
3398 VREV32:24:result_int8x8 [] = { fffffff3, fffffff2, fffffff1, fffffff0, fffffff7, fffffff6, fffffff5…
3399 VREV32:25:result_int16x4 [] = { fffffff1, fffffff0, fffffff3, fffffff2, }
3400 VREV32:26:result_int32x2 [] = { 33333333, 33333333, }
3401 VREV32:27:result_int64x1 [] = { 3333333333333333, }
3402 VREV32:28:result_uint8x8 [] = { f3, f2, f1, f0, f7, f6, f5, f4, }
3403 VREV32:29:result_uint16x4 [] = { fff1, fff0, fff3, fff2, }
3404 VREV32:30:result_uint32x2 [] = { 33333333, 33333333, }
3405 VREV32:31:result_uint64x1 [] = { 3333333333333333, }
3406 VREV32:32:result_poly8x8 [] = { f3, f2, f1, f0, f7, f6, f5, f4, }
[all …]
Dref-rvct-all.txt3397 VREV32 output:
3398 VREV32:24:result_int8x8 [] = { fffffff3, fffffff2, fffffff1, fffffff0, fffffff7, fffffff6, fffffff5…
3399 VREV32:25:result_int16x4 [] = { fffffff1, fffffff0, fffffff3, fffffff2, }
3400 VREV32:26:result_int32x2 [] = { 33333333, 33333333, }
3401 VREV32:27:result_int64x1 [] = { 3333333333333333, }
3402 VREV32:28:result_uint8x8 [] = { f3, f2, f1, f0, f7, f6, f5, f4, }
3403 VREV32:29:result_uint16x4 [] = { fff1, fff0, fff3, fff2, }
3404 VREV32:30:result_uint32x2 [] = { 33333333, 33333333, }
3405 VREV32:31:result_uint64x1 [] = { 3333333333333333, }
3406 VREV32:32:result_poly8x8 [] = { f3, f2, f1, f0, f7, f6, f5, f4, }
[all …]
Dexpected_input4gcc-nofp16.txt3038 VREV32 output:
Dexpected_input4gcc.txt3244 VREV32 output:
/external/llvm/lib/Target/ARM/
DARMISelLowering.h154 VREV32, // reverse elements within 32-bit words enumerator
DARMScheduleSwift.td549 (instregex "VEXT", "VREV16", "VREV32", "VREV64")>;
DARMISelLowering.cpp1209 case ARMISD::VREV32: return "ARMISD::VREV32"; in getTargetNodeName()
4767 SDValue N0 = DAG.getNode(ARMISD::VREV32, DL, VT16Bit, Counts16); in lowerCTPOP32BitElements()
6146 return DAG.getNode(ARMISD::VREV32, dl, VT, OpLHS); in GeneratePerfectShuffle()
6271 return DAG.getNode(ARMISD::VREV32, dl, VT, V1); in LowerVECTOR_SHUFFLE()
DARMInstrNEON.td575 def NEONvrev32 : SDNode<"ARMISD::VREV32", SDTARMVSHUF>;
6287 // VREV32 : Vector Reverse elements within 32-bit words
/external/clang/include/clang/Basic/
Darm_neon.td784 def VREV32 : WOpInst<"vrev32", "dd", "csUcUsPcPsQcQsQUcQUsQPcQPs", OP_REV32>;