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Searched refs:VREV64 (Results 1 – 24 of 24) sorted by relevance

/external/libxaac/decoder/armv7/
Dixheaacd_dec_DCT2_64_asm.s51 VREV64.32 Q1, Q1
88 VREV64.32 Q2, Q2
91 VREV64.32 Q3, Q3
99 VREV64.16 D10, D10
120 VREV64.32 Q2, Q2
125 VREV64.32 Q3, Q3
136 VREV64.32 Q7, Q7
137 VREV64.32 Q6, Q6
140 VREV64.16 D10, D10
164 VREV64.32 Q2, Q2
[all …]
Dixheaacd_overlap_add2.s56 VREV64.16 D4, D6
57 VREV64.16 D5, D7
71 VREV64.16 Q6, Q7
85 VREV64.16 D4, D6
87 VREV64.16 D5, D7
106 VREV64.16 Q6, Q7
160 VREV64.32 D0, D6
161 VREV64.32 D1, D7
166 VREV64.16 D2, D2
167 VREV64.16 D3, D3
[all …]
Dixheaacd_dct3_32.s57 VREV64.32 Q1, Q1
74 VREV64.32 Q4, Q4
89 VREV64.32 Q1, Q1
119 VREV64.32 Q4, Q4
136 VREV64.32 Q1, Q1
152 VREV64.32 Q4, Q4
291 VREV64.32 Q2, Q2
294 VREV64.32 Q3, Q3
307 VREV64.16 D8, D8
343 VREV64.32 Q13, Q13
[all …]
Dixheaacd_pre_twiddle_compute.s111 VREV64.16 Q5, Q4
116 VREV64.16 Q0, Q0
117 VREV64.16 Q2, Q2
168 VREV64.16 Q5, Q4
178 VREV64.16 Q0, Q0
181 VREV64.16 Q2, Q2
237 VREV64.16 Q5, Q4
244 VREV64.16 Q0, Q0
247 VREV64.16 Q2, Q2
326 VREV64.16 Q0, Q0
[all …]
Dixheaacd_no_lap1.s48 VREV64.32 Q13, Q13
67 VREV64.32 Q10, Q10
79 VREV64.32 Q13, Q13
99 VREV64.32 Q10, Q10
Dixheaacd_post_twiddle.s110 VREV64.16 Q6, Q4
168 VREV64.16 Q6, Q4
191 VREV64.32 Q7, Q7
204 VREV64.32 Q12, Q12
276 VREV64.16 Q6, Q4
299 VREV64.32 Q7, Q7
310 VREV64.32 Q12, Q12
399 VREV64.32 Q7, Q7
410 VREV64.32 Q12, Q12
435 VREV64.16 Q6, Q4
[all …]
Dixheaacd_overlap_add1.s49 VREV64.32 Q3, Q3
60 VREV64.16 Q1, Q1
106 VREV64.32 Q3, Q3
115 VREV64.16 Q1, Q1
149 VREV64.32 Q3, Q3
168 VREV64.16 Q1, Q1
212 VREV64.32 Q3, Q3
220 VREV64.16 Q1, Q1
Dixheaacd_mps_synt_post_fft_twiddle.s56 VREV64.32 D1, D1
57 VREV64.32 D0, D0
Dixheaacd_post_twiddle_overlap.s195 VREV64.16 Q0, Q0
196 VREV64.16 Q1, Q1
220 VREV64.16 Q5, Q5
223 VREV64.16 Q6, Q6
391 VREV64.16 Q0, Q0
394 VREV64.16 Q1, Q1
408 VREV64.16 Q5, Q5
411 VREV64.16 Q6, Q6
654 VREV64.16 Q0, Q0
657 VREV64.16 Q1, Q1
[all …]
Dixheaacd_calc_pre_twid.s44 VREV64.32 D8, D8
45 VREV64.32 D9, D10
/external/swiftshader/third_party/LLVM/lib/Target/ARM/
DARMISelLowering.h155 VREV64, // reverse elements within 64-bit doublewords enumerator
DARMISelLowering.cpp905 case ARMISD::VREV64: return "ARMISD::VREV64"; in getTargetNodeName()
4270 return DAG.getNode(ARMISD::VREV64, dl, VT, OpLHS); in GeneratePerfectShuffle()
4367 return DAG.getNode(ARMISD::VREV64, dl, VT, V1); in LowerVECTOR_SHUFFLE()
DARMInstrNEON.td131 def NEONvrev64 : SDNode<"ARMISD::VREV64", SDTARMVSHUF>;
4683 // VREV64 : Vector Reverse elements within 64-bit doublewords
/external/swiftshader/third_party/LLVM/test/CodeGen/ARM/
Dvrev.ll151 ; vrev <4 x i16> should use VREV32 and not VREV64
/external/arm-neon-tests/
Dref-rvct-neon-nofp16.txt2999 VREV64 output:
3000 VREV64:44:result_int8x8 [] = { fffffff7, fffffff6, fffffff5, fffffff4, fffffff3, fffffff2, fffffff1…
3001 VREV64:45:result_int16x4 [] = { fffffff3, fffffff2, fffffff1, fffffff0, }
3002 VREV64:46:result_int32x2 [] = { fffffff1, fffffff0, }
3003 VREV64:47:result_int64x1 [] = { 3333333333333333, }
3004 VREV64:48:result_uint8x8 [] = { f7, f6, f5, f4, f3, f2, f1, f0, }
3005 VREV64:49:result_uint16x4 [] = { fff3, fff2, fff1, fff0, }
3006 VREV64:50:result_uint32x2 [] = { fffffff1, fffffff0, }
3007 VREV64:51:result_uint64x1 [] = { 3333333333333333, }
3008 VREV64:52:result_poly8x8 [] = { f7, f6, f5, f4, f3, f2, f1, f0, }
[all …]
Dref-rvct-neon.txt3423 VREV64 output:
3424 VREV64:48:result_int8x8 [] = { fffffff7, fffffff6, fffffff5, fffffff4, fffffff3, fffffff2, fffffff1…
3425 VREV64:49:result_int16x4 [] = { fffffff3, fffffff2, fffffff1, fffffff0, }
3426 VREV64:50:result_int32x2 [] = { fffffff1, fffffff0, }
3427 VREV64:51:result_int64x1 [] = { 3333333333333333, }
3428 VREV64:52:result_uint8x8 [] = { f7, f6, f5, f4, f3, f2, f1, f0, }
3429 VREV64:53:result_uint16x4 [] = { fff3, fff2, fff1, fff0, }
3430 VREV64:54:result_uint32x2 [] = { fffffff1, fffffff0, }
3431 VREV64:55:result_uint64x1 [] = { 3333333333333333, }
3432 VREV64:56:result_poly8x8 [] = { f7, f6, f5, f4, f3, f2, f1, f0, }
[all …]
Dref-rvct-all.txt3423 VREV64 output:
3424 VREV64:48:result_int8x8 [] = { fffffff7, fffffff6, fffffff5, fffffff4, fffffff3, fffffff2, fffffff1…
3425 VREV64:49:result_int16x4 [] = { fffffff3, fffffff2, fffffff1, fffffff0, }
3426 VREV64:50:result_int32x2 [] = { fffffff1, fffffff0, }
3427 VREV64:51:result_int64x1 [] = { 3333333333333333, }
3428 VREV64:52:result_uint8x8 [] = { f7, f6, f5, f4, f3, f2, f1, f0, }
3429 VREV64:53:result_uint16x4 [] = { fff3, fff2, fff1, fff0, }
3430 VREV64:54:result_uint32x2 [] = { fffffff1, fffffff0, }
3431 VREV64:55:result_uint64x1 [] = { 3333333333333333, }
3432 VREV64:56:result_poly8x8 [] = { f7, f6, f5, f4, f3, f2, f1, f0, }
[all …]
Dexpected_input4gcc-nofp16.txt3062 VREV64 output:
Dexpected_input4gcc.txt3270 VREV64 output:
/external/llvm/lib/Target/ARM/
DARMISelLowering.h153 VREV64, // reverse elements within 64-bit doublewords enumerator
DARMScheduleSwift.td549 (instregex "VEXT", "VREV16", "VREV32", "VREV64")>;
DARMISelLowering.cpp1208 case ARMISD::VREV64: return "ARMISD::VREV64"; in getTargetNodeName()
4489 DAG.getNode(ARMISD::VREV64, dl, SrcVT, Op)); in ExpandBITCAST()
6143 return DAG.getNode(ARMISD::VREV64, dl, VT, OpLHS); in GeneratePerfectShuffle()
6206 OpLHS = DAG.getNode(ARMISD::VREV64, DL, VT, OpLHS); in LowerReverse_VECTOR_SHUFFLEv16i8_v8i16()
6269 return DAG.getNode(ARMISD::VREV64, dl, VT, V1); in LowerVECTOR_SHUFFLE()
DARMInstrNEON.td574 def NEONvrev64 : SDNode<"ARMISD::VREV64", SDTARMVSHUF>;
6264 // VREV64 : Vector Reverse elements within 64-bit doublewords
/external/clang/include/clang/Basic/
Darm_neon.td782 def VREV64 : WOpInst<"vrev64", "dd", "csiUcUsUiPcPsfQcQsQiQUcQUsQUiQPcQPsQf",