Searched refs:VRegInfo (Results 1 – 5 of 5) sorted by relevance
22 VRegInfo.reserve(256); in MachineRegisterInfo()34 assert(VRegInfo[TargetRegisterInfo::index2VirtReg(i)].second == 0 && in ~MachineRegisterInfo()47 VRegInfo[Reg].first = RC; in setRegClass()107 void *ArrayBase = getNumVirtRegs() == 0 ? 0 : &VRegInfo[FirstVirtReg]; in createVirtualRegister()108 VRegInfo.grow(Reg); in createVirtualRegister()109 VRegInfo[Reg].first = RegClass; in createVirtualRegister()112 if (ArrayBase && &VRegInfo[FirstVirtReg] != ArrayBase) in createVirtualRegister()126 MachineOperand *List = VRegInfo[Reg].second; in HandleVRegListReallocation()129 List->Contents.Reg.Prev = &VRegInfo[Reg].second; in HandleVRegListReallocation()
54 struct VRegInfo { struct107 const VRegInfo &RegInfo) const;121 VRegInfo *VRegInfos;210 VRegInfo &MORegInfo = VRegInfos[MORegIdx]; in addUsedLanesOnOperand()303 VRegInfo &RegInfo = VRegInfos[DefRegIdx]; in transferDefinedLanesStep()462 const VRegInfo &RegInfo) const { in isUndefRegAtInput()483 const VRegInfo &DefRegInfo = VRegInfos[DefRegIdx]; in isUndefInput()503 VRegInfo &Info = VRegInfos[RegIdx]; in runOnce()513 VRegInfo &Info = VRegInfos[RegIdx]; in runOnce()529 const VRegInfo &Info = VRegInfos[RegIdx]; in runOnce()[all …]
30 VRegInfo.reserve(256); in MachineRegisterInfo()41 VRegInfo[Reg].first = RC; in setRegClass()46 VRegInfo[Reg].first = &RegBank; in setRegBank()102 VRegInfo.grow(Reg); in createVirtualRegister()103 VRegInfo[Reg].first = RegClass; in createVirtualRegister()126 VRegInfo.grow(Reg); in createGenericVirtualRegister()128 VRegInfo[Reg].first = static_cast<TargetRegisterClass *>(nullptr); in createGenericVirtualRegister()141 if (!VRegInfo[Reg].second) in clearVirtRegs()147 VRegInfo.clear(); in clearVirtRegs()
39 VirtReg2IndexFunctor> VRegInfo; variable180 return VRegInfo[RegNo].second; in getRegUseDefListHead()186 return VRegInfo[RegNo].second; in getRegUseDefListHead()212 return VRegInfo[Reg].first; in getRegClass()247 unsigned getNumVirtRegs() const { return VRegInfo.size(); } in getNumVirtRegs()
62 VRegInfo; variable81 return VRegInfo[RegNo].second; in getRegUseDefListHead()87 return VRegInfo[RegNo].second; in getRegUseDefListHead()575 assert(VRegInfo[Reg].first.is<const TargetRegisterClass *>() && in getRegClass()577 return VRegInfo[Reg].first.get<const TargetRegisterClass *>(); in getRegClass()592 const RegClassOrRegBank &Val = VRegInfo[Reg].first; in getRegClassOrNull()602 const RegClassOrRegBank &Val = VRegInfo[Reg].first; in getRegBankOrNull()611 return VRegInfo[Reg].first; in getRegClassOrRegBank()663 unsigned getNumVirtRegs() const { return VRegInfo.size(); } in getNumVirtRegs()