Searched refs:VRegs (Results 1 – 15 of 15) sorted by relevance
| /external/llvm/lib/Target/AArch64/ |
| D | AArch64CallLowering.cpp | 58 const SmallVectorImpl<unsigned> &VRegs) const { in lowerFormalArguments()
85 MIRBuilder.buildInstr(TargetOpcode::COPY, VRegs[i], VA.getLocReg()); in lowerFormalArguments()
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| D | AArch64CallLowering.h | 33 const SmallVectorImpl<unsigned> &VRegs) const override;
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| D | AArch64InstrAtomics.td | 370 // The fast register allocator used during -O0 inserts spills to cover any VRegs
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| /external/swiftshader/third_party/LLVM/lib/CodeGen/ |
| D | RegAllocBasic.cpp | 191 LiveVirtRegBitSet &VRegs = unionVRegs[PhysReg]; in verify() local
192 PhysReg2LiveUnion[PhysReg].verify(VRegs); in verify()
195 assert(!VisitedVRegs.intersects(VRegs) && "vreg in multiple unions"); in verify()
196 VisitedVRegs |= VRegs; in verify()
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| /external/llvm/lib/Target/AMDGPU/ |
| D | AMDGPUCallLowering.cpp | 39 const SmallVectorImpl<unsigned> &VRegs) const { in lowerFormalArguments()
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| D | AMDGPUCallLowering.h | 33 const SmallVectorImpl<unsigned> &VRegs) const override;
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| /external/llvm/include/llvm/CodeGen/GlobalISel/ |
| D | CallLowering.h | 66 const SmallVectorImpl<unsigned> &VRegs) const { in lowerFormalArguments() argument
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| /external/capstone/arch/PowerPC/ |
| D | PPCDisassembler.c | 63 static const unsigned VRegs[] = { variable
193 return decodeRegisterClass(Inst, RegNo, VRegs); in DecodeVRRCRegisterClass()
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| /external/swiftshader/third_party/LLVM/lib/Target/PowerPC/ |
| D | PPCFrameLowering.cpp | 813 SmallVector<CalleeSavedInfo, 18> VRegs; in processFunctionBeforeFrameFinalized() local
850 VRegs.push_back(CSI[i]); in processFunctionBeforeFrameFinalized()
963 for (unsigned i = 0, e = VRegs.size(); i != e; ++i) { in processFunctionBeforeFrameFinalized()
964 int FI = VRegs[i].getFrameIdx(); in processFunctionBeforeFrameFinalized()
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| /external/llvm/lib/Target/Hexagon/ |
| D | HexagonFrameLowering.h | 136 SmallVectorImpl<unsigned> &VRegs) const;
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| D | HexagonFrameLowering.cpp | 1860 SmallVectorImpl<unsigned> &VRegs) const { in optimizeSpillSlots()
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| /external/llvm/lib/Target/PowerPC/Disassembler/ |
| D | PPCDisassembler.cpp | 92 static const unsigned VRegs[] = { variable
248 return decodeRegisterClass(Inst, RegNo, VRegs); in DecodeVRRCRegisterClass()
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| /external/llvm/lib/Target/PowerPC/ |
| D | PPCFrameLowering.cpp | 1485 SmallVector<CalleeSavedInfo, 18> VRegs; in processFunctionBeforeFrameFinalized() local
1521 VRegs.push_back(CSI[i]); in processFunctionBeforeFrameFinalized()
1661 for (unsigned i = 0, e = VRegs.size(); i != e; ++i) { in processFunctionBeforeFrameFinalized()
1662 int FI = VRegs[i].getFrameIdx(); in processFunctionBeforeFrameFinalized()
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| /external/llvm/lib/Target/PowerPC/AsmParser/ |
| D | PPCAsmParser.cpp | 86 static const MCPhysReg VRegs[32] = { variable
601 Inst.addOperand(MCOperand::createReg(VRegs[getReg()])); in addRegVRRCOperands()
1297 RegNo = VRegs[IntVal]; in MatchRegisterName()
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| /external/llvm/lib/Target/ARM/ |
| D | ARMInstrInfo.td | 5817 // The fast register allocator used during -O0 inserts spills to cover any VRegs
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