/external/libxaac/decoder/armv7/ |
D | ixheaacd_sbr_imdct_using_fft.s | 398 VTRN.32 q12, q5 401 VTRN.32 q9, q2 405 VTRN.32 q0, q7 409 VTRN.32 q14, q4 413 VTRN.32 q13, q6 417 VTRN.32 q10, q3 421 VTRN.32 q1, q8 425 VTRN.32 q15, q11 579 VTRN.32 q0, q4 582 VTRN.32 q2, q6 [all …]
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D | ixheaacd_imdct_using_fft.s | 394 VTRN.32 q12, q5 396 VTRN.32 q9, q2 400 VTRN.32 q0, q7 404 VTRN.32 q14, q4 408 VTRN.32 q13, q6 412 VTRN.32 q10, q3 416 VTRN.32 q1, q8 420 VTRN.32 q15, q11 570 VTRN.32 q0, q4 573 VTRN.32 q2, q6 [all …]
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D | ixheaacd_fft32x32_ld.s | 402 VTRN.32 q12, q5 405 VTRN.32 q9, q2 409 VTRN.32 q0, q7 413 VTRN.32 q14, q4 417 VTRN.32 q13, q6 421 VTRN.32 q10, q3 425 VTRN.32 q1, q8 429 VTRN.32 q15, q11 583 VTRN.32 q0, q4 586 VTRN.32 q2, q6 [all …]
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D | ixheaacd_esbr_cos_sin_mod_loop2.s | 99 VTRN.32 D2, D3
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/external/arm-neon-tests/ |
D | ref-rvct-neon-nofp16.txt | 3047 VTRN/VTRNQ chunk 0 output: 3048 VTRN/VTRNQ:0:result_int8x8 [] = { fffffff0, fffffff1, 11, 11, fffffff2, fffffff3, 11, 11, } 3049 VTRN/VTRNQ:1:result_int16x4 [] = { fffffff0, fffffff1, 22, 22, } 3050 VTRN/VTRNQ:2:result_int32x2 [] = { fffffff0, fffffff1, } 3051 VTRN/VTRNQ:3:result_int64x1 [] = { 3333333333333333, } 3052 VTRN/VTRNQ:4:result_uint8x8 [] = { f0, f1, 55, 55, f2, f3, 55, 55, } 3053 VTRN/VTRNQ:5:result_uint16x4 [] = { fff0, fff1, 66, 66, } 3054 VTRN/VTRNQ:6:result_uint32x2 [] = { fffffff0, fffffff1, } 3055 VTRN/VTRNQ:7:result_uint64x1 [] = { 3333333333333333, } 3056 VTRN/VTRNQ:8:result_poly8x8 [] = { f0, f1, 55, 55, f2, f3, 55, 55, } [all …]
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D | ref-rvct-neon.txt | 3475 VTRN/VTRNQ chunk 0 output: 3476 VTRN/VTRNQ:0:result_int8x8 [] = { fffffff0, fffffff1, 11, 11, fffffff2, fffffff3, 11, 11, } 3477 VTRN/VTRNQ:1:result_int16x4 [] = { fffffff0, fffffff1, 22, 22, } 3478 VTRN/VTRNQ:2:result_int32x2 [] = { fffffff0, fffffff1, } 3479 VTRN/VTRNQ:3:result_int64x1 [] = { 3333333333333333, } 3480 VTRN/VTRNQ:4:result_uint8x8 [] = { f0, f1, 55, 55, f2, f3, 55, 55, } 3481 VTRN/VTRNQ:5:result_uint16x4 [] = { fff0, fff1, 66, 66, } 3482 VTRN/VTRNQ:6:result_uint32x2 [] = { fffffff0, fffffff1, } 3483 VTRN/VTRNQ:7:result_uint64x1 [] = { 3333333333333333, } 3484 VTRN/VTRNQ:8:result_poly8x8 [] = { f0, f1, 55, 55, f2, f3, 55, 55, } [all …]
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D | ref-rvct-all.txt | 3475 VTRN/VTRNQ chunk 0 output: 3476 VTRN/VTRNQ:0:result_int8x8 [] = { fffffff0, fffffff1, 11, 11, fffffff2, fffffff3, 11, 11, } 3477 VTRN/VTRNQ:1:result_int16x4 [] = { fffffff0, fffffff1, 22, 22, } 3478 VTRN/VTRNQ:2:result_int32x2 [] = { fffffff0, fffffff1, } 3479 VTRN/VTRNQ:3:result_int64x1 [] = { 3333333333333333, } 3480 VTRN/VTRNQ:4:result_uint8x8 [] = { f0, f1, 55, 55, f2, f3, 55, 55, } 3481 VTRN/VTRNQ:5:result_uint16x4 [] = { fff0, fff1, 66, 66, } 3482 VTRN/VTRNQ:6:result_uint32x2 [] = { fffffff0, fffffff1, } 3483 VTRN/VTRNQ:7:result_uint64x1 [] = { 3333333333333333, } 3484 VTRN/VTRNQ:8:result_poly8x8 [] = { f0, f1, 55, 55, f2, f3, 55, 55, } [all …]
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D | expected_input4gcc-nofp16.txt | 3110 VTRN/VTRNQ chunk 0 output: 3134 VTRN/VTRNQ chunk 1 output:
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/external/llvm/test/MC/ARM/ |
D | neon-shuffle-encoding.s | 79 @ VTRN alternate size suffices
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/external/swiftshader/third_party/LLVM/test/CodeGen/ARM/ |
D | vzip.ll | 27 ; VZIP.32 is equivalent to VTRN.32 for 64-bit vectors.
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D | vuzp.ll | 27 ; VUZP.32 is equivalent to VTRN.32 for 64-bit vectors.
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D | vtrn.ll | 99 ; Undef shuffle indices should not prevent matching to VTRN:
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/external/llvm/test/CodeGen/AArch64/ |
D | arm64-trn.ll | 108 ; Undef shuffle indices should not prevent matching to VTRN:
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/external/swiftshader/third_party/LLVM/lib/Target/ARM/ |
D | ARMISelLowering.h | 160 VTRN, // transpose enumerator
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D | ARMISelLowering.cpp | 910 case ARMISD::VTRN: return "ARMISD::VTRN"; in getTargetNodeName() 4299 return DAG.getNode(ARMISD::VTRN, dl, DAG.getVTList(VT, VT), in GeneratePerfectShuffle() 4380 return DAG.getNode(ARMISD::VTRN, dl, DAG.getVTList(VT, VT), in LowerVECTOR_SHUFFLE() 4390 return DAG.getNode(ARMISD::VTRN, dl, DAG.getVTList(VT, VT), in LowerVECTOR_SHUFFLE()
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D | ARMInstrNEON.td | 140 def NEONtrn : SDNode<"ARMISD::VTRN", SDTARMVSHUF2>; 1879 // 2-register shuffles (VTRN/VZIP/VUZP), both double- and quad-register. 4814 // VTRN : Vector Transpose
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D | ARMISelDAGToDAG.cpp | 2682 case ARMISD::VTRN: { in Select()
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/external/llvm/lib/Target/ARM/ |
D | ARMISelLowering.h | 158 VTRN, // transpose enumerator
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D | ARMScheduleSwift.td | 584 (instregex "VSWP", "VTRN", "VUZP", "VZIP")>;
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D | ARMISelLowering.cpp | 1213 case ARMISD::VTRN: return "ARMISD::VTRN"; in getTargetNodeName() 5593 return ARMISD::VTRN; in isNEONTwoResultShuffleMask() 5601 return ARMISD::VTRN; in isNEONTwoResultShuffleMask() 6172 return DAG.getNode(ARMISD::VTRN, dl, DAG.getVTList(VT, VT), in GeneratePerfectShuffle()
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D | ARMISelDAGToDAG.cpp | 3105 case ARMISD::VTRN: { in Select()
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D | ARMInstrNEON.td | 583 def NEONtrn : SDNode<"ARMISD::VTRN", SDTARMVSHUF2>; 2532 // 2-register shuffles (VTRN/VZIP/VUZP), both double- and quad-register. 6404 // VTRN : Vector Transpose
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/external/llvm/test/CodeGen/ARM/ |
D | vzip.ll | 67 ; VZIP.32 is equivalent to VTRN.32 for 64-bit vectors.
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D | vuzp.ll | 67 ; VUZP.32 is equivalent to VTRN.32 for 64-bit vectors.
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/external/clang/include/clang/Basic/ |
D | arm_neon.td | 813 def VTRN : WInst<"vtrn", "2dd", "csiUcUsUifPcPsQcQsQiQUcQUsQUiQfQPcQPs">;
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