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Searched refs:VectorFormat (Results 1 – 9 of 9) sorted by relevance

/external/vixl/src/aarch64/
Dsimulator-aarch64.h373 int64_t Int(VectorFormat vform, int index) const { in Int()
395 uint64_t Uint(VectorFormat vform, int index) const { in Uint()
417 uint64_t UintLeftJustified(VectorFormat vform, int index) const { in UintLeftJustified()
421 int64_t IntLeftJustified(VectorFormat vform, int index) const { in IntLeftJustified()
428 void SetInt(VectorFormat vform, int index, int64_t value) const { in SetInt()
448 void SetIntArray(VectorFormat vform, const int64_t* src) const { in SetIntArray()
455 void SetUint(VectorFormat vform, int index, uint64_t value) const { in SetUint()
475 void SetUintArray(VectorFormat vform, const uint64_t* src) const { in SetUintArray()
482 void ReadUintFromMem(VectorFormat vform, int index, uint64_t addr) const { in ReadUintFromMem()
502 void WriteUintToMem(VectorFormat vform, int index, uint64_t addr) const { in WriteUintToMem()
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Dlogic-aarch64.cc402 void Simulator::ld1(VectorFormat vform, LogicVRegister dst, uint64_t addr) { in ld1()
411 void Simulator::ld1(VectorFormat vform, in ld1()
419 void Simulator::ld1r(VectorFormat vform, LogicVRegister dst, uint64_t addr) { in ld1r()
427 void Simulator::ld2(VectorFormat vform, in ld2()
444 void Simulator::ld2(VectorFormat vform, in ld2()
457 void Simulator::ld2r(VectorFormat vform, in ld2r()
471 void Simulator::ld3(VectorFormat vform, in ld3()
493 void Simulator::ld3(VectorFormat vform, in ld3()
510 void Simulator::ld3r(VectorFormat vform, in ld3r()
528 void Simulator::ld4(VectorFormat vform, in ld4()
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Dinstructions-aarch64.cc396 VectorFormat VectorFormatHalfWidth(VectorFormat vform) { in VectorFormatHalfWidth()
419 VectorFormat VectorFormatDoubleWidth(VectorFormat vform) { in VectorFormatDoubleWidth()
442 VectorFormat VectorFormatFillQ(VectorFormat vform) { in VectorFormatFillQ()
466 VectorFormat VectorFormatHalfWidthDoubleLanes(VectorFormat vform) { in VectorFormatHalfWidthDoubleLanes()
486 VectorFormat VectorFormatDoubleLanes(VectorFormat vform) { in VectorFormatDoubleLanes()
502 VectorFormat VectorFormatHalfLanes(VectorFormat vform) { in VectorFormatHalfLanes()
518 VectorFormat ScalarFormatFromLaneSize(int laneSize) { in ScalarFormatFromLaneSize()
535 VectorFormat ScalarFormatFromFormat(VectorFormat vform) { in ScalarFormatFromFormat()
540 unsigned RegisterSizeInBitsFromFormat(VectorFormat vform) { in RegisterSizeInBitsFromFormat()
562 unsigned RegisterSizeInBytesFromFormat(VectorFormat vform) { in RegisterSizeInBytesFromFormat()
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Dinstructions-aarch64.h506 enum VectorFormat { enum
530 VectorFormat VectorFormatHalfWidth(VectorFormat vform);
531 VectorFormat VectorFormatDoubleWidth(VectorFormat vform);
532 VectorFormat VectorFormatDoubleLanes(VectorFormat vform);
533 VectorFormat VectorFormatHalfLanes(VectorFormat vform);
534 VectorFormat ScalarFormatFromLaneSize(int lanesize);
535 VectorFormat VectorFormatHalfWidthDoubleLanes(VectorFormat vform);
536 VectorFormat VectorFormatFillQ(VectorFormat vform);
537 VectorFormat ScalarFormatFromFormat(VectorFormat vform);
538 unsigned RegisterSizeInBitsFromFormat(VectorFormat vform);
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Dsimulator-aarch64.cc521 VectorFormat vform) { in GetPrintRegisterFormat()
556 VectorFormat vform) { in GetPrintRegisterFormatFP()
2623 VectorFormat vform = (instr->Mask(FP64) == FP64) ? kFormatD : kFormatS; in VisitFPDataProcessing1Source()
2715 VectorFormat vform = (instr->Mask(FP64) == FP64) ? kFormatD : kFormatS; in VisitFPDataProcessing2Source()
2990 VectorFormat vf = nfd.GetVectorFormat(); in VisitNEON2RegMisc()
2994 VectorFormat vf_lp = nfd.GetVectorFormat(&map_lp); in VisitNEON2RegMisc()
2997 VectorFormat vf_fcvtl = nfd.GetVectorFormat(&map_fcvtl); in VisitNEON2RegMisc()
3001 VectorFormat vf_fcvtn = nfd.GetVectorFormat(&map_fcvtn); in VisitNEON2RegMisc()
3088 VectorFormat fpf = nfd.GetVectorFormat(nfd.FPFormatMap()); in VisitNEON2RegMisc()
3257 VectorFormat vf = nfd.GetVectorFormat(nfd.LogicalFormatMap()); in VisitNEON3Same()
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Doperands-aarch64.h314 VRegister(unsigned code, VectorFormat format) in VRegister()
Dassembler-aarch64.cc3233 (vd_index < LaneCountFromFormat(static_cast<VectorFormat>(format)))); in ins()
3236 (vn_index < LaneCountFromFormat(static_cast<VectorFormat>(format)))); in ins()
3277 (vd_index < LaneCountFromFormat(static_cast<VectorFormat>(format)))); in ins()
3316 (vn_index < LaneCountFromFormat(static_cast<VectorFormat>(format)))); in umov()
3350 (vn_index < LaneCountFromFormat(static_cast<VectorFormat>(format)))); in smov()
Dassembler-aarch64.h3018 int s = LaneSizeInBytesLog2FromFormat(static_cast<VectorFormat>(format)); in ImmNEON5()
3025 int s = LaneSizeInBytesLog2FromFormat(static_cast<VectorFormat>(format)); in ImmNEON4()
/external/vixl/test/aarch64/
Dtest-simulator-aarch64.cc1302 VectorFormat vd_form, in Test1OpNEON_Helper()
1303 VectorFormat vn_form) { in Test1OpNEON_Helper()
1389 VectorFormat vd_form, in Test1OpNEON()
1390 VectorFormat vn_form) { in Test1OpNEON()
1500 VectorFormat vd_form, in Test1OpAcrossNEON_Helper()
1501 VectorFormat vn_form) { in Test1OpAcrossNEON_Helper()
1592 VectorFormat vd_form, in Test1OpAcrossNEON()
1593 VectorFormat vn_form) { in Test1OpAcrossNEON()
1723 VectorFormat vd_form, in Test2OpNEON_Helper()
1724 VectorFormat vn_form, in Test2OpNEON_Helper()
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