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Searched refs:ZERO_EXTEND (Results 1 – 25 of 78) sorted by relevance

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/external/llvm/lib/Target/X86/
DX86TargetTransformInfo.cpp565 { ISD::ZERO_EXTEND, MVT::v16i32, MVT::v16i1, 2 }, in getCastInstrCost()
567 { ISD::ZERO_EXTEND, MVT::v16i32, MVT::v16i8, 1 }, in getCastInstrCost()
569 { ISD::ZERO_EXTEND, MVT::v16i32, MVT::v16i16, 1 }, in getCastInstrCost()
570 { ISD::ZERO_EXTEND, MVT::v8i64, MVT::v8i16, 1 }, in getCastInstrCost()
573 { ISD::ZERO_EXTEND, MVT::v8i64, MVT::v8i32, 1 }, in getCastInstrCost()
618 { ISD::ZERO_EXTEND, MVT::v4i64, MVT::v4i1, 3 }, in getCastInstrCost()
620 { ISD::ZERO_EXTEND, MVT::v8i32, MVT::v8i1, 3 }, in getCastInstrCost()
622 { ISD::ZERO_EXTEND, MVT::v4i64, MVT::v4i8, 3 }, in getCastInstrCost()
624 { ISD::ZERO_EXTEND, MVT::v8i32, MVT::v8i8, 3 }, in getCastInstrCost()
626 { ISD::ZERO_EXTEND, MVT::v16i16, MVT::v16i8, 1 }, in getCastInstrCost()
[all …]
DX86ISelLowering.cpp689 setOperationAction(ISD::ZERO_EXTEND, VT, Expand); in X86TargetLowering()
1000 setOperationAction(ISD::ZERO_EXTEND, MVT::v4i64, Custom); in X86TargetLowering()
1001 setOperationAction(ISD::ZERO_EXTEND, MVT::v8i32, Custom); in X86TargetLowering()
1002 setOperationAction(ISD::ZERO_EXTEND, MVT::v16i16, Custom); in X86TargetLowering()
1248 setOperationAction(ISD::ZERO_EXTEND, MVT::v4i32, Custom); in X86TargetLowering()
1249 setOperationAction(ISD::ZERO_EXTEND, MVT::v2i64, Custom); in X86TargetLowering()
1267 setOperationAction(ISD::ZERO_EXTEND, MVT::v16i32, Custom); in X86TargetLowering()
1268 setOperationAction(ISD::ZERO_EXTEND, MVT::v8i64, Custom); in X86TargetLowering()
1447 setOperationAction(ISD::ZERO_EXTEND, MVT::v32i8, Custom); in X86TargetLowering()
1449 setOperationAction(ISD::ZERO_EXTEND, MVT::v32i16, Custom); in X86TargetLowering()
[all …]
/external/llvm/lib/Target/AArch64/
DAArch64TargetTransformInfo.cpp198 { ISD::ZERO_EXTEND, MVT::v4i64, MVT::v4i16, 3 }, in getCastInstrCost()
200 { ISD::ZERO_EXTEND, MVT::v4i64, MVT::v4i32, 2 }, in getCastInstrCost()
202 { ISD::ZERO_EXTEND, MVT::v8i32, MVT::v8i8, 3 }, in getCastInstrCost()
204 { ISD::ZERO_EXTEND, MVT::v8i32, MVT::v8i16, 2 }, in getCastInstrCost()
206 { ISD::ZERO_EXTEND, MVT::v8i64, MVT::v8i8, 7 }, in getCastInstrCost()
208 { ISD::ZERO_EXTEND, MVT::v8i64, MVT::v8i16, 6 }, in getCastInstrCost()
210 { ISD::ZERO_EXTEND, MVT::v16i16, MVT::v16i8, 2 }, in getCastInstrCost()
212 { ISD::ZERO_EXTEND, MVT::v16i32, MVT::v16i8, 6 }, in getCastInstrCost()
/external/llvm/lib/Target/ARM/
DARMTargetTransformInfo.cpp106 { ISD::ZERO_EXTEND, MVT::v4i32, MVT::v4i16, 0 }, in getCastInstrCost()
108 { ISD::ZERO_EXTEND, MVT::v2i64, MVT::v2i32, 1 }, in getCastInstrCost()
114 { ISD::ZERO_EXTEND, MVT::v4i64, MVT::v4i16, 3 }, in getCastInstrCost()
116 { ISD::ZERO_EXTEND, MVT::v8i32, MVT::v8i8, 3 }, in getCastInstrCost()
118 { ISD::ZERO_EXTEND, MVT::v8i64, MVT::v8i8, 7 }, in getCastInstrCost()
120 { ISD::ZERO_EXTEND, MVT::v8i64, MVT::v8i16, 6 }, in getCastInstrCost()
122 { ISD::ZERO_EXTEND, MVT::v16i32, MVT::v16i8, 6 }, in getCastInstrCost()
DARMSelectionDAGInfo.cpp94 Src = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, Src); in EmitSpecializedLibcall()
/external/llvm/lib/Target/NVPTX/
DNVPTXISelLowering.cpp1172 Elt = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i16, Elt); in LowerCall()
1187 Elt0 = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i16, Elt0); in LowerCall()
1188 Elt1 = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i16, Elt1); in LowerCall()
1232 StoreVal = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i16, StoreVal); in LowerCall()
1239 DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i16, StoreVal); in LowerCall()
1251 DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i16, StoreVal); in LowerCall()
1261 DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i16, StoreVal); in LowerCall()
1302 unsigned opc = ISD::ZERO_EXTEND; in LowerCall()
2022 Tmp3 = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i16, Tmp3); in LowerSTOREi1()
2401 StoreVal = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i16, StoreVal); in LowerReturn()
[all …]
/external/swiftshader/third_party/LLVM/lib/CodeGen/SelectionDAG/
DDAGCombiner.cpp713 Op.getValueType().isByteSized() ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND; in PromoteOperand()
1080 case ISD::ZERO_EXTEND: return visitZERO_EXTEND(N); in visit()
1153 case ISD::ZERO_EXTEND: in combine()
1474 SDValue ZExt = DAG.getNode(ISD::ZERO_EXTEND, DL, VT, N0.getOperand(0)); in visitADD()
2038 N0 = DAG.getNode(ISD::ZERO_EXTEND, DL, NewVT, N0); in visitMULHU()
2039 N1 = DAG.getNode(ISD::ZERO_EXTEND, DL, NewVT, N1); in visitMULHU()
2150 SDValue Lo = DAG.getNode(ISD::ZERO_EXTEND, DL, NewVT, N->getOperand(0)); in visitUMUL_LOHI()
2151 SDValue Hi = DAG.getNode(ISD::ZERO_EXTEND, DL, NewVT, N->getOperand(1)); in visitUMUL_LOHI()
2219 if ((N0.getOpcode() == ISD::ZERO_EXTEND || in SimplifyBinOpWithSameOpcodeHands()
2302 SDValue Zext = DAG.getNode(ISD::ZERO_EXTEND, N->getDebugLoc(), in visitAND()
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DTargetLowering.cpp1019 ExtendKind = ISD::ZERO_EXTEND; in GetReturnInfo()
1192 SDValue Z = DAG.getNode(ISD::ZERO_EXTEND, dl, Op.getValueType(), X); in ShrinkDemandedOp()
1636 case ISD::ZERO_EXTEND: { in SimplifyDemandedBits()
1685 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::ZERO_EXTEND, dl, in SimplifyDemandedBits()
1798 Sign = TLO.DAG.getNode(ISD::ZERO_EXTEND, dl, Op.getValueType(), Sign); in SimplifyDemandedBits()
1984 if (N0->getOpcode() == ISD::ZERO_EXTEND) { in SimplifySetCC()
2074 if (N0.getOpcode() == ISD::ZERO_EXTEND) { in SimplifySetCC()
2577 N0 = DAG.getNode(ISD::ZERO_EXTEND, dl, VT, N0); in SimplifySetCC()
DLegalizeDAG.cpp664 unsigned CastOpc = IdxVT.bitsGT(PtrVT) ? ISD::TRUNCATE : ISD::ZERO_EXTEND; in PerformInsertVectorEltInMemory()
1363 case ISD::ZEXTLOAD: ExtendOp = ISD::ZERO_EXTEND; break; in LegalizeOp()
1775 Idx = DAG.getNode(ISD::ZERO_EXTEND, dl, TLI.getPointerTy(), Idx); in ExpandExtractFromVectorThroughStack()
1818 Idx = DAG.getNode(ISD::ZERO_EXTEND, dl, TLI.getPointerTy(), Idx); in ExpandInsertToVectorThroughStack()
2682 DAG.getNode(isSigned ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND, in PromoteLegalINT_TO_FP()
3607 { { ISD::MULHU, ISD::UMUL_LOHI, ISD::ZERO_EXTEND }, in ExpandNode()
3678 Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, dl, PairTy, Node->getOperand(0)); in ExpandNode()
3841 Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, dl, NVT, Node->getOperand(0)); in PromoteNode()
3861 Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, dl, NVT, Node->getOperand(0)); in PromoteNode()
3945 ExtOp = isSignedIntSetCC(CCCode) ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND; in PromoteNode()
DLegalizeIntegerTypes.cpp93 case ISD::ZERO_EXTEND: in PromoteIntegerResult()
289 unsigned Opc = VT.isByteSized() ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND; in PromoteIntRes_Constant()
399 if (N->getOpcode() == ISD::ZERO_EXTEND) in PromoteIntRes_INT_EXTEND()
713 SDValue Res = DAG.getNode(ISD::ZERO_EXTEND, dl, NVT, Parts[0]); in PromoteIntRes_VAARG()
715 SDValue Part = DAG.getNode(ISD::ZERO_EXTEND, dl, NVT, Parts[i]); in PromoteIntRes_VAARG()
782 case ISD::ZERO_EXTEND: Res = PromoteIntOp_ZERO_EXTEND(N); break; in PromoteIntegerOperand()
1115 case ISD::ZERO_EXTEND: ExpandIntRes_ZERO_EXTEND(N, Lo, Hi); break; in ExpandIntegerResult()
2368 Lo = DAG.getNode(ISD::ZERO_EXTEND, dl, NVT, N->getOperand(0)); in ExpandIntRes_ZERO_EXTEND()
DLegalizeVectorOps.cpp166 case ISD::ZERO_EXTEND: in LegalizeOp()
DSelectionDAG.cpp898 getNode(ISD::ZERO_EXTEND, DL, VT, Op) : in getZExtOrTrunc()
1449 ISD::NodeType Opcode = OpTy.bitsGT(ShTy) ? ISD::TRUNCATE : ISD::ZERO_EXTEND; in getShiftAmountOperand()
1869 case ISD::ZERO_EXTEND: { in ComputeMaskedBits()
2402 case ISD::ZERO_EXTEND: in getNode()
2504 if (OpOpcode == ISD::SIGN_EXTEND || OpOpcode == ISD::ZERO_EXTEND) in getNode()
2510 case ISD::ZERO_EXTEND: in getNode()
2520 if (OpOpcode == ISD::ZERO_EXTEND) // (zext (zext x)) -> (zext x) in getNode()
2521 return getNode(ISD::ZERO_EXTEND, DL, VT, in getNode()
2538 if (OpOpcode == ISD::ZERO_EXTEND || OpOpcode == ISD::SIGN_EXTEND || in getNode()
2564 else if (OpOpcode == ISD::ZERO_EXTEND || OpOpcode == ISD::SIGN_EXTEND || in getNode()
[all …]
DLegalizeTypes.cpp989 Index = DAG.getNode(ISD::ZERO_EXTEND, dl, TLI.getPointerTy(), Index); in GetVectorElementPointer()
1009 Lo = DAG.getNode(ISD::ZERO_EXTEND, dlLo, NVT, Lo); in JoinIntegers()
/external/swiftshader/third_party/LLVM/include/llvm/CodeGen/
DISDOpcodes.h362 ZERO_EXTEND, enumerator
/external/llvm/include/llvm/CodeGen/
DISDOpcodes.h395 ZERO_EXTEND, enumerator
/external/swiftshader/third_party/LLVM/lib/Target/ARM/
DARMSelectionDAGInfo.cpp172 Src = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, Src); in EmitTargetCodeForMemset()
/external/llvm/lib/CodeGen/SelectionDAG/
DDAGCombiner.cpp983 Op.getValueType().isByteSized() ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND; in PromoteOperand()
1396 case ISD::ZERO_EXTEND: return visitZERO_EXTEND(N); in visit()
1485 case ISD::ZERO_EXTEND: in combine()
1762 SDValue ZExt = DAG.getNode(ISD::ZERO_EXTEND, DL, VT, N0.getOperand(0)); in visitADD()
2531 N0 = DAG.getNode(ISD::ZERO_EXTEND, DL, NewVT, N0); in visitMULHU()
2532 N1 = DAG.getNode(ISD::ZERO_EXTEND, DL, NewVT, N1); in visitMULHU()
2640 SDValue Lo = DAG.getNode(ISD::ZERO_EXTEND, DL, NewVT, N->getOperand(0)); in visitUMUL_LOHI()
2641 SDValue Hi = DAG.getNode(ISD::ZERO_EXTEND, DL, NewVT, N->getOperand(1)); in visitUMUL_LOHI()
2721 if ((N0.getOpcode() == ISD::ZERO_EXTEND || in SimplifyBinOpWithSameOpcodeHands()
2999 return DAG.getNode(ISD::ZERO_EXTEND, SL, VT, And); in visitANDLike()
[all …]
DLegalizeDAG.cpp1478 SignBit = DAG.getNode(ISD::ZERO_EXTEND, DL, MagVT, SignBit); in ExpandFCOPYSIGN()
2507 DAG.getNode(isSigned ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND, in PromoteLegalINT_TO_FP()
2845 case ISD::ZERO_EXTEND: in ExpandNode()
2848 RHS = DAG.getNode(ISD::ZERO_EXTEND, dl, OuterType, Node->getOperand(2)); in ExpandNode()
2853 RHS = DAG.getNode(ISD::ZERO_EXTEND, dl, OuterType, Node->getOperand(2)); in ExpandNode()
3307 if (TLI.isOperationLegalOrCustom(ISD::ZERO_EXTEND, VT) && in ExpandNode()
3312 Lo = DAG.getNode(ISD::ZERO_EXTEND, dl, VT, Lo); in ExpandNode()
3384 { { ISD::MULHU, ISD::UMUL_LOHI, ISD::ZERO_EXTEND }, in ExpandNode()
3465 Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, dl, PairTy, Node->getOperand(0)); in ExpandNode()
4016 Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, dl, NVT, Node->getOperand(0)); in PromoteNode()
[all …]
DTargetLowering.cpp413 SDValue Z = DAG.getNode(NeedZext ? ISD::ZERO_EXTEND : ISD::ANY_EXTEND, in ShrinkDemandedOp()
959 case ISD::ZERO_EXTEND: { in SimplifyDemandedBits()
1008 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::ZERO_EXTEND, dl, in SimplifyDemandedBits()
1125 Sign = TLO.DAG.getNode(ISD::ZERO_EXTEND, dl, Op.getValueType(), Sign); in SimplifyDemandedBits()
1430 if (N0->getOpcode() == ISD::ZERO_EXTEND) { in SimplifySetCC()
1488 (N0Opc == ISD::ZERO_EXTEND || N0Opc == ISD::SIGN_EXTEND) && in SimplifySetCC()
1569 if (N0.getOpcode() == ISD::ZERO_EXTEND) { in SimplifySetCC()
2173 N0 = DAG.getNode(ISD::ZERO_EXTEND, dl, VT, N0); in SimplifySetCC()
/external/swiftshader/third_party/LLVM/lib/Target/Blackfin/
DBlackfinISelLowering.cpp263 Opi = DAG.getNode(ISD::ZERO_EXTEND, dl, VA.getLocVT(), Opi); in LowerReturn()
320 Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, VA.getLocVT(), Arg); in LowerCall()
/external/swiftshader/third_party/LLVM/lib/Target/CellSPU/
DSPUISelLowering.cpp451 setTargetDAGCombine(ISD::ZERO_EXTEND); in SPUTargetLowering()
729 result = DAG.getNode(ISD::ZERO_EXTEND, dl, OutVT, result); in LowerLOAD()
2094 Elt = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, Elt); in LowerEXTRACT_VECTOR_ELT()
2229 N0 = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i16, N0); in LowerI8Math()
2232 ? ISD::ZERO_EXTEND in LowerI8Math()
2252 N0 = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i16, N0); in LowerI8Math()
2254 unsigned N1Opc = ISD::ZERO_EXTEND; in LowerI8Math()
2967 case ISD::ZERO_EXTEND: in PerformDAGCombine()
3042 case ISD::ZERO_EXTEND: in PerformDAGCombine()
/external/llvm/lib/Target/SystemZ/
DSystemZISelDAGToDAG.cpp681 if (Index.getOpcode() == ISD::ZERO_EXTEND) in selectBDVAddr12Only()
825 case ISD::ZERO_EXTEND: in expandRxSBG()
1272 case ISD::ZERO_EXTEND: in Select()
/external/swiftshader/third_party/LLVM/lib/Target/X86/
DX86FastISel.cpp772 unsigned Op = Outs[0].Flags.isZExt() ? ISD::ZERO_EXTEND : in X86SelectRet()
986 ResultReg = FastEmit_r(MVT::i8, DstVT.getSimpleVT(), ISD::ZERO_EXTEND, in X86SelectZExt()
1690 bool Emitted = X86FastEmitExtend(ISD::ZERO_EXTEND, VA.getLocVT(), in DoSelectCall()
1702 Emitted = X86FastEmitExtend(ISD::ZERO_EXTEND, VA.getLocVT(), in DoSelectCall()
DX86ISelLowering.cpp738 setOperationAction(ISD::ZERO_EXTEND, (MVT::SimpleValueType)VT, Expand); in X86TargetLowering()
1155 setTargetDAGCombine(ISD::ZERO_EXTEND); in X86TargetLowering()
1532 if (Subtarget->is64Bit() && VT == MVT::i1 && ExtendKind == ISD::ZERO_EXTEND) in getTypeForExtArgOrReturn()
2131 Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, RegVT, Arg); in LowerCall()
4829 LastElt = DAG.getNode(ISD::ZERO_EXTEND, dl, in LowerBuildVectorv16i8()
4833 ThisElt = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i16, Op.getOperand(i)); in LowerBuildVectorv16i8()
5154 Item = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, Item); in LowerBUILD_VECTOR()
9233 return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC); in LowerINTRINSIC_WO_CHAIN()
9311 return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC); in LowerINTRINSIC_WO_CHAIN()
9712 ISD::TRUNCATE : ISD::ZERO_EXTEND), DL, VT, RetVal); in LowerFLT_ROUNDS_()
[all …]
/external/swiftshader/third_party/LLVM/lib/Target/SystemZ/
DSystemZISelLowering.cpp419 Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, VA.getLocVT(), Arg); in LowerCCCCallTo()
591 ResValue = DAG.getNode(ISD::ZERO_EXTEND, dl, VA.getLocVT(), ResValue); in LowerReturn()

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