| /external/mesa3d/src/gallium/drivers/vc4/kernel/ |
| D | vc4_validate_shaders.c | 116 uint32_t add_a = QPU_GET_FIELD(inst, QPU_ADD_A); in raddr_add_a_to_live_reg_index() local
120 if (add_a == QPU_MUX_A) in raddr_add_a_to_live_reg_index()
122 else if (add_a == QPU_MUX_B && sig != QPU_SIG_SMALL_IMM) in raddr_add_a_to_live_reg_index()
124 else if (add_a <= QPU_MUX_R3) in raddr_add_a_to_live_reg_index()
125 return 64 + add_a; in raddr_add_a_to_live_reg_index()
476 uint32_t add_a = QPU_GET_FIELD(inst, QPU_ADD_A); in track_live_clamps() local
519 (add_a != QPU_MUX_B && add_b != QPU_MUX_B)) { in track_live_clamps()
|
| /external/llvm/test/MC/Mips/ |
| D | mips-reginfo-fp64.s | 59 add_a.b $w26,$w26,$w26
60 add_a.b $w27,$w27,$w27
|
| /external/mesa3d/src/gallium/drivers/vc4/ |
| D | vc4_qpu.c | 407 uint32_t add_a = QPU_GET_FIELD(*inst, QPU_ADD_A); in convert_mov() local
413 (add_a != QPU_GET_FIELD(*inst, QPU_ADD_B))) { in convert_mov()
427 *inst = QPU_UPDATE_FIELD(*inst, add_a, QPU_MUL_A); in convert_mov()
428 *inst = QPU_UPDATE_FIELD(*inst, add_a, QPU_MUL_B); in convert_mov()
|
| D | vc4_qpu_schedule.c | 358 uint32_t add_a = QPU_GET_FIELD(inst, QPU_ADD_A); in calculate_deps() local
372 process_mux_deps(state, n, add_a); in calculate_deps()
|
| /external/capstone/suite/MC/Mips/ |
| D | test_3r.s.cs | 2 0x78,0x04,0x4e,0x90 = add_a.b $w26, $w9, $w4
3 0x78,0x3f,0xdd,0xd0 = add_a.h $w23, $w27, $w31
4 0x78,0x56,0x32,0xd0 = add_a.w $w11, $w6, $w22
5 0x78,0x60,0x51,0x90 = add_a.d $w6, $w10, $w0
|
| /external/llvm/test/MC/Mips/msa/ |
| D | test_3r.s | 3 # CHECK: add_a.b $w26, $w9, $w4 # encoding: [0x78,0x04,0x4e,0x90]
4 # CHECK: add_a.h $w23, $w27, $w31 # encoding: [0x78,0x3f,0xdd,0xd0]
5 # CHECK: add_a.w $w11, $w6, $w22 # encoding: [0x78,0x56,0x32,0xd0]
6 # CHECK: add_a.d $w6, $w10, $w0 # encoding: [0x78,0x60,0x51,0x90]
246 add_a.b $w26, $w9, $w4
247 add_a.h $w23, $w27, $w31
248 add_a.w $w11, $w6, $w22
249 add_a.d $w6, $w10, $w0
|
| /external/swiftshader/third_party/LLVM/test/CodeGen/Blackfin/ |
| D | inline-asm.ll | 19 define i32 @add_a(i32 %A, i32 %B) {
|
| /external/llvm/test/MC/Disassembler/Mips/msa/ |
| D | test_3r.txt | 3 0x78 0x04 0x4e 0x90 # CHECK: add_a.b $w26, $w9, $w4
4 0x78 0x3f 0xdd 0xd0 # CHECK: add_a.h $w23, $w27, $w31
5 0x78 0x56 0x32 0xd0 # CHECK: add_a.w $w11, $w6, $w22
6 0x78 0x60 0x51 0x90 # CHECK: add_a.d $w6, $w10, $w0
|
| /external/llvm/test/Transforms/LoopVectorize/AArch64/ |
| D | loop-vectorization-factors.ll | 6 ; CHECK-LABEL: @add_a(
11 define void @add_a(i8* noalias nocapture readonly %p, i8* noalias nocapture %q, i32 %len) #0 {
|
| /external/llvm/test/CodeGen/Mips/msa/ |
| D | 3r-a.ll | 32 ; CHECK-DAG: add_a.b [[WD:\$w[0-9]+]], [[WS]], [[WT]]
57 ; CHECK-DAG: add_a.h [[WD:\$w[0-9]+]], [[WS]], [[WT]]
82 ; CHECK-DAG: add_a.w [[WD:\$w[0-9]+]], [[WS]], [[WT]]
107 ; CHECK-DAG: add_a.d [[WD:\$w[0-9]+]], [[WS]], [[WT]]
|
| /external/llvm/lib/Target/Mips/ |
| D | MipsMSAInstrInfo.td | 1487 class ADD_A_B_DESC : MSA_3R_DESC_BASE<"add_a.b", int_mips_add_a_b, MSA128BOpnd>,
1489 class ADD_A_H_DESC : MSA_3R_DESC_BASE<"add_a.h", int_mips_add_a_h, MSA128HOpnd>,
1491 class ADD_A_W_DESC : MSA_3R_DESC_BASE<"add_a.w", int_mips_add_a_w, MSA128WOpnd>,
1493 class ADD_A_D_DESC : MSA_3R_DESC_BASE<"add_a.d", int_mips_add_a_d, MSA128DOpnd>,
|