| /external/python/cpython3/Lib/test/decimaltestdata/ |
| D | dqAnd.decTest | 9 -- These testcases are experimental ('beta' versions), and they --
15 -- Please send comments, suggestions, and corrections to the author: --
30 dqand001 and 0 0 -> 0
31 dqand002 and 0 1 -> 0
32 dqand003 and 1 0 -> 0
33 dqand004 and 1 1 -> 1
34 dqand005 and 1100 1010 -> 1000
35 -- and at msd and msd-1
37 dqand006 and 0000000000000000000000000000000000 0000000000000000000000000000000000 -> …
38 dqand007 and 0000000000000000000000000000000000 1000000000000000000000000000000000 -> …
[all …]
|
| D | ddAnd.decTest | 9 -- These testcases are experimental ('beta' versions), and they --
15 -- Please send comments, suggestions, and corrections to the author: --
30 ddand001 and 0 0 -> 0
31 ddand002 and 0 1 -> 0
32 ddand003 and 1 0 -> 0
33 ddand004 and 1 1 -> 1
34 ddand005 and 1100 1010 -> 1000
35 -- and at msd and msd-1
37 ddand006 and 0000000000000000 0000000000000000 -> 0
38 ddand007 and 0000000000000000 1000000000000000 -> 0
[all …]
|
| D | and.decTest | 2 -- and.decTest -- digitwise logical AND --
9 -- These testcases are experimental ('beta' versions), and they --
15 -- Please send comments, suggestions, and corrections to the author: --
29 andx001 and 0 0 -> 0
30 andx002 and 0 1 -> 0
31 andx003 and 1 0 -> 0
32 andx004 and 1 1 -> 1
33 andx005 and 1100 1010 -> 1000
34 andx006 and 1111 10 -> 10
35 andx007 and 1111 1010 -> 1010
[all …]
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| /external/python/cpython2/Lib/test/decimaltestdata/ |
| D | dqAnd.decTest | 9 -- These testcases are experimental ('beta' versions), and they --
15 -- Please send comments, suggestions, and corrections to the author: --
30 dqand001 and 0 0 -> 0
31 dqand002 and 0 1 -> 0
32 dqand003 and 1 0 -> 0
33 dqand004 and 1 1 -> 1
34 dqand005 and 1100 1010 -> 1000
35 -- and at msd and msd-1
37 dqand006 and 0000000000000000000000000000000000 0000000000000000000000000000000000 -> …
38 dqand007 and 0000000000000000000000000000000000 1000000000000000000000000000000000 -> …
[all …]
|
| D | ddAnd.decTest | 9 -- These testcases are experimental ('beta' versions), and they --
15 -- Please send comments, suggestions, and corrections to the author: --
30 ddand001 and 0 0 -> 0
31 ddand002 and 0 1 -> 0
32 ddand003 and 1 0 -> 0
33 ddand004 and 1 1 -> 1
34 ddand005 and 1100 1010 -> 1000
35 -- and at msd and msd-1
37 ddand006 and 0000000000000000 0000000000000000 -> 0
38 ddand007 and 0000000000000000 1000000000000000 -> 0
[all …]
|
| D | and.decTest | 2 -- and.decTest -- digitwise logical AND --
9 -- These testcases are experimental ('beta' versions), and they --
15 -- Please send comments, suggestions, and corrections to the author: --
29 andx001 and 0 0 -> 0
30 andx002 and 0 1 -> 0
31 andx003 and 1 0 -> 0
32 andx004 and 1 1 -> 1
33 andx005 and 1100 1010 -> 1000
34 andx006 and 1111 10 -> 10
35 andx007 and 1111 1010 -> 1010
[all …]
|
| /external/swiftshader/third_party/LLVM/test/CodeGen/CellSPU/ |
| D | select_bits.ll | 11 ; (or (and rC, rB), (and (not rC), rA))
13 %C = and <2 x i64> %rC, %rB
15 %B = and <2 x i64> %A, %rA
20 ; (or (and rB, rC), (and (not rC), rA))
22 %C = and <2 x i64> %rB, %rC
24 %B = and <2 x i64> %A, %rA
29 ; (or (and (not rC), rA), (and rB, rC))
32 %B = and <2 x i64> %A, %rA
33 %C = and <2 x i64> %rB, %rC
38 ; (or (and (not rC), rA), (and rC, rB))
[all …]
|
| /external/v8/ |
| D | ChangeLog | 3 Performance and stability improvements on all platforms.
8 Performance and stability improvements on all platforms.
13 Performance and stability improvements on all platforms.
18 Performance and stability improvements on all platforms.
23 Performance and stability improvements on all platforms.
28 Performance and stability improvements on all platforms.
33 Performance and stability improvements on all platforms.
38 Performance and stability improvements on all platforms.
43 Performance and stability improvements on all platforms.
48 Performance and stability improvements on all platforms.
[all …]
|
| /external/llvm/test/CodeGen/SystemZ/ |
| D | risbg-01.ll | 12 %and = and i32 %shr, 1
13 ret i32 %and
16 ; ...and again with i64.
22 %and = and i64 %shr, 1
23 ret i64 %and
32 %and = and i32 %shr, 12
33 ret i32 %and
36 ; ...and again with i64.
42 %and = and i64 %shr, 12
43 ret i64 %and
[all …]
|
| D | and-02.ll | 10 %and = and i32 %a, 1
11 ret i32 %and
19 %and = and i32 %b, 1
20 ret i32 %and
28 %and = and i32 %b, 4
29 ret i32 %and
37 %and = and i32 %a, 5
38 ret i32 %and
46 %and = and i32 %b, 5
47 ret i32 %and
[all …]
|
| D | and-04.ll | 10 %and = and i64 %a, 1
11 ret i64 %and
19 %and = and i64 %a, 65534
20 ret i64 %and
28 %and = and i64 %b, 65535
29 ret i64 %and
37 %and = and i64 %a, 65536
38 ret i64 %and
46 %and = and i64 %a, 4294967294
47 ret i64 %and
[all …]
|
| D | rnsbg-01.ll | 11 %and = and i32 %a, %orb
12 ret i32 %and
15 ; ...and again with i64.
21 %and = and i64 %a, %orb
22 ret i64 %and
31 %and = and i32 %a, %orb
32 ret i32 %and
35 ; ...and again with i64.
41 %and = and i64 %a, %orb
42 ret i64 %and
[all …]
|
| /external/scapy/scapy/contrib/ |
| D | gtp_v2.uts | 10 gtp.dport == 2123 and gtp.gtp_type == 1
14 gtp.dport == 2123 and gtp.seq == 12345 and gtp.gtp_type == 1 and gtp.T == 0
20 gtp.dport == 2123 and gtp.teid == 2807 and gtp.seq == 12345
45 ie.ietype == 1 and ie.IMSI == b'2080112345670000'
56 ie.ietype == 2 and ie.Cause == 16 and ie.PCE == 1 and ie.BCE == 0 and ie.CS == 0
61 ie.ietype == 2 and ie.Cause == 16 and ie.PCE == 0 and ie.BCE == 1 and ie.CS == 0
66 ie.ietype == 2 and ie.Cause == 16 and ie.PCE == 0 and ie.BCE == 0 and ie.CS == 1
72 ie.ietype == 3 and ie.restart_counter == 13
77 ie.ietype == 3 and ie.restart_counter == 17
87 ie.ietype == 71 and ie.APN == b'aaaaaaaaaaaaaaaaaaaaaaaaa'
[all …]
|
| D | gtp.uts | 21 gtp.dport == 2123 and gtp.teid == 2807 and len(gtp.IE_list) == 5
44 ie.ietype == 1 and ie.CauseValue == 128
48 ie.ietype == 1 and ie.CauseValue == 194
54 ie.ietype == 2 and ie.imsi == b'2080112345670000'
58 ie.ietype == 2 and ie.imsi == b'208103397660354'
64 ie.ietype == 3 and ie.MCC == b'234' and ie.MNC == b'02' and ie.LAC == 1234 and ie.RAC == 123
68 ie.ietype == 3 and ie.MCC == b'234' and ie.MNC == b'02' and ie.LAC == 1234 and ie.RAC == 123
74 ie.ietype == 14 and ie.restart_counter == 14
78 ie.ietype == 14 and ie.restart_counter == 14
84 ie.ietype == 15 and ie.SelectionMode == 252
[all …]
|
| /external/swiftshader/third_party/LLVM/test/Transforms/InstCombine/ |
| D | bit-checks.ll | 8 %and = and i32 %argc, 1 ; <i32> [#uses=1]
9 %tobool = icmp ne i32 %and, 0 ; <i1> [#uses=1]
10 %and2 = and i32 %argc, 2 ; <i32> [#uses=1]
12 %or.cond = and i1 %tobool, %tobool3 ; <i1> [#uses=1]
19 %and = and i32 %argc, 1 ; <i32> [#uses=1]
20 %tobool = icmp eq i32 %and, 0 ; <i1> [#uses=1]
21 %and2 = and i32 %argc, 2 ; <i32> [#uses=1]
35 %and = and i32 %argc, 7 ; <i32> [#uses=1]
36 %tobool = icmp eq i32 %and, 0 ; <i1> [#uses=1]
37 %and2 = and i32 %argc, 48 ; <i32> [#uses=1]
[all …]
|
| /external/llvm/test/Transforms/InstCombine/ |
| D | bit-checks.ll | 8 %and = and i32 %argc, 1 ; <i32> [#uses=1]
9 %tobool = icmp ne i32 %and, 0 ; <i1> [#uses=1]
10 %and2 = and i32 %argc, 2 ; <i32> [#uses=1]
12 %or.cond = and i1 %tobool, %tobool3 ; <i1> [#uses=1]
19 %and = and i32 %argc, 1 ; <i32> [#uses=1]
20 %tobool = icmp eq i32 %and, 0 ; <i1> [#uses=1]
21 %and2 = and i32 %argc, 2 ; <i32> [#uses=1]
35 %and = and i32 %argc, 7 ; <i32> [#uses=1]
36 %tobool = icmp eq i32 %and, 0 ; <i1> [#uses=1]
37 %and2 = and i32 %argc, 48 ; <i32> [#uses=1]
[all …]
|
| /external/llvm/test/CodeGen/AArch64/ |
| D | tbi.ll | 7 ; TBI-NOT: and x
8 ; NO_TBI: and x
10 %and = and i64 %p, 72057594037927935
11 %cast = inttoptr i64 %and to i32*
18 ; TBI-NOT: and x
19 ; NO_TBI: and x
21 %and = and i64 %p, 72057594037927935
22 %cast = inttoptr i64 %and to i32*
30 ; TBI-NOT: and x
31 ; NO_TBI: and x
[all …]
|
| /external/llvm/test/CodeGen/AMDGPU/ |
| D | and.ll | 18 %result = and <2 x i32> %a, %b
38 %result = and <4 x i32> %a, %b
46 %and = and i32 %a, %b
47 store i32 %and, i32 addrspace(1)* %out, align 4
54 %and = and i32 %a, 1234567
55 store i32 %and, i32 addrspace(1)* %out, align 4
60 ; can fold into the s_and_b32 and the VALU one is materialized
70 %and = and i32 %a, 1234567
73 %foo = add i32 %and, %b
87 %and = and i32 %a, 1234567
[all …]
|
| /external/tensorflow/tensorflow/docs_src/about/ |
| D | bib.md | 10 algorithms, and an implementation for executing such algorithms.
14 and tablets up to large-scale distributed systems of hundreds
15 of machines and thousands of computational devices such as
16 GPU cards. The system is flexible and can be used to express
17 a wide variety of algorithms, including training and inference
18 algorithms for deep neural network models, and it has been
19 used for conducting research and for deploying machine learning
21 computer science and other fields, including speech recognition,
23 language processing, geographic information extraction, and
25 interface and an implementation of that interface that
[all …]
|
| /external/icu/icu4c/source/data/rbnf/ |
| D | mt.txt | 1 // © 2016 and later: Unicode, Inc. and others.
75 "1000: elf[>%%and-type-b-masculine>];",
76 "2000: elfejn[>%%and-type-b-masculine>];",
77 "3000: <%%thousands< elef[>%%and-type-b-masculine>];",
78 "11000/1000: <%spellout-cardinal-masculine< elf[>%%and-type-b-masculine>];",
79 "1000000: miljun[>%%and-type-b-masculine>];",
80 "2000000: <%spellout-cardinal-masculine< miljuni[>%%and-type-b-masculine>];",
81 "11000000/1,000: <%spellout-cardinal-masculine< miljun[>%%and-type-b-masculine>];",
82 "1000000000: biljun[>%%and-type-b-masculine>];",
83 "2000000000: <%spellout-cardinal-masculine< biljuni[>%%and-type-b-masculine>];",
[all …]
|
| /external/llvm/test/Transforms/InstSimplify/ |
| D | select.ll | 4 %and = and i32 %x, 1
5 %cmp = icmp eq i32 %and, 0
6 %and1 = and i32 %x, -2
14 %and = and i32 %x, 1
15 %cmp = icmp ne i32 %and, 0
16 %and1 = and i32 %x, -2
24 %and = and i32 %x, 1
25 %cmp = icmp ne i32 %and, 0
26 %and1 = and i32 %x, -2
30 ; CHECK: %[[and:.*]] = and i32 %x, -2
[all …]
|
| /external/llvm/test/Transforms/LoopUnswitch/ |
| D | exponential-behavior.ll | 12 %us.0 = and i1 %unswitch_cond_root, %unswitch_cond_root
13 %us.1 = and i1 %us.0, %us.0
14 %us.2 = and i1 %us.1, %us.1
15 %us.3 = and i1 %us.2, %us.2
16 %us.4 = and i1 %us.3, %us.3
17 %us.5 = and i1 %us.4, %us.4
18 %us.6 = and i1 %us.5, %us.5
19 %us.7 = and i1 %us.6, %us.6
20 %us.8 = and i1 %us.7, %us.7
21 %us.9 = and i1 %us.8, %us.8
[all …]
|
| /external/icu/icu4j/main/tests/core/src/com/ibm/icu/dev/test/duration/testdata/ |
| D | testdata_en.txt | 167 1 hour and 5 minutes
169 1 hour and 10 minutes
171 1 hour and 15 minutes
173 1 hour and 20 minutes
175 1 hour and 25 minutes
177 1 hour and 30 minutes
179 1 hour and 35 minutes
181 1 hour and 40 minutes
183 1 hour and 45 minutes
185 1 hour and 50 minutes
[all …]
|
| /external/icu/android_icu4j/src/main/tests/android/icu/dev/test/duration/testdata/ |
| D | testdata_en.txt | 167 1 hour and 5 minutes
169 1 hour and 10 minutes
171 1 hour and 15 minutes
173 1 hour and 20 minutes
175 1 hour and 25 minutes
177 1 hour and 30 minutes
179 1 hour and 35 minutes
181 1 hour and 40 minutes
183 1 hour and 45 minutes
185 1 hour and 50 minutes
[all …]
|
| /external/llvm/test/CodeGen/PowerPC/ |
| D | bperm.ll | 44 %and = and i64 %0, 5963776000
45 ret i64 %and
51 ; CHECK: and 3, [[REG3]], [[REG2]]
58 %and = and i64 %0, 133434808670355456
59 ret i64 %and
67 ; CHECK: and 3, [[REG5]], [[REG4]]
74 %and = and i64 %0, 191795733152661504
75 ret i64 %and
82 ; CHECK: and 3, [[REG4]], [[REG3]]
89 %and = and i64 %0, 58195968
[all …]
|