Searched refs:array_mode (Results 1 – 9 of 9) sorted by relevance
| /external/mesa3d/src/amd/addrlib/inc/chip/r800/ |
| D | si_gb_reg.h | 98 unsigned int array_mode : 4; member
130 unsigned int array_mode : 4; member
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| /external/mesa3d/src/gallium/drivers/nouveau/nv50/ |
| D | nv50_state_validate.c | 26 uint32_t array_size = 0xffff, array_mode = 0; in nv50_validate_fb() local
52 array_mode = NV50_3D_RT_ARRAY_MODE_MODE_3D; /* 1 << 16 */ in nv50_validate_fb()
55 assert(mt->layout_3d || !array_mode || array_size == 1); in nv50_validate_fb()
70 PUSH_DATA (push, array_mode | array_size); in nv50_validate_fb()
71 nv50->rt_array_mode = array_mode | array_size; in nv50_validate_fb()
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| /external/mesa3d/src/gallium/drivers/radeonsi/ |
| D | si_dma.c | 147 unsigned array_mode, lbpp, pitch_tile_max, slice_tile_max, size; in si_dma_copy_tile() local
169 array_mode = G_009910_ARRAY_MODE(tile_mode); in si_dma_copy_tile()
205 radeon_emit(cs, (detile << 31) | (array_mode << 27) | in si_dma_copy_tile()
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| /external/mesa3d/src/gallium/drivers/r600/ |
| D | r600_state.c | 670 unsigned char swizzle[4], array_mode = 0; in r600_create_sampler_view_custom() local
739 array_mode = V_038000_ARRAY_LINEAR_ALIGNED; in r600_create_sampler_view_custom()
742 array_mode = V_038000_ARRAY_1D_TILED_THIN1; in r600_create_sampler_view_custom()
745 array_mode = V_038000_ARRAY_2D_TILED_THIN1; in r600_create_sampler_view_custom()
751 S_038000_TILE_MODE(array_mode) | in r600_create_sampler_view_custom()
1022 unsigned level, pitch, slice, format, offset, array_mode; in r600_init_depth_surface() local
1033 array_mode = V_0280A0_ARRAY_2D_TILED_THIN1; in r600_init_depth_surface()
1038 array_mode = V_0280A0_ARRAY_1D_TILED_THIN1; in r600_init_depth_surface()
1045 surf->db_depth_info = S_028010_ARRAY_MODE(array_mode) | S_028010_FORMAT(format); in r600_init_depth_surface()
2823 unsigned array_mode, lbpp, pitch_tile_max, slice_tile_max, size; in r600_dma_copy_tile() local
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| D | evergreen_state.c | 668 unsigned char swizzle[4], array_mode = 0, non_disp_tiling = 0; in evergreen_create_sampler_view_custom() local
760 array_mode = V_028C70_ARRAY_LINEAR_ALIGNED; in evergreen_create_sampler_view_custom()
763 array_mode = V_028C70_ARRAY_2D_TILED_THIN1; in evergreen_create_sampler_view_custom()
766 array_mode = V_028C70_ARRAY_1D_TILED_THIN1; in evergreen_create_sampler_view_custom()
817 S_030004_ARRAY_MODE(array_mode)); in evergreen_create_sampler_view_custom()
1172 unsigned format, array_mode; in evergreen_init_depth_surface() local
1184 array_mode = V_028C70_ARRAY_2D_TILED_THIN1; in evergreen_init_depth_surface()
1189 array_mode = V_028C70_ARRAY_1D_TILED_THIN1; in evergreen_init_depth_surface()
1203 surf->db_z_info = S_028040_ARRAY_MODE(array_mode) | in evergreen_init_depth_surface()
3355 unsigned array_mode, lbpp, pitch_tile_max, slice_tile_max, size; in evergreen_dma_copy_tile() local
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| /external/mesa3d/src/gallium/drivers/radeon/ |
| D | r600_texture.c | 193 enum radeon_surf_mode array_mode, in r600_init_surface() argument
225 array_mode == RADEON_SURF_MODE_2D) { in r600_init_surface()
260 array_mode, surface); in r600_init_surface()
1241 unsigned array_mode; in r600_texture_from_handle() local
1266 array_mode = RADEON_SURF_MODE_2D; in r600_texture_from_handle()
1268 array_mode = RADEON_SURF_MODE_1D; in r600_texture_from_handle()
1270 array_mode = RADEON_SURF_MODE_LINEAR_ALIGNED; in r600_texture_from_handle()
1272 r = r600_init_surface(rscreen, &surface, templ, array_mode, stride, in r600_texture_from_handle()
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| /external/mesa3d/src/amd/vulkan/ |
| D | radv_image.c | 56 unsigned array_mode = radv_choose_tiling(device, create_info); in radv_init_surface() local
79 surface->flags = RADEON_SURF_SET(array_mode, MODE); in radv_init_surface()
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| /external/mesa3d/src/amd/addrlib/r800/ |
| D | ciaddrlib.cpp | 1250 UINT_32 regArrayMode = gbTileMode.f.array_mode; in ReadGbTileMode()
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| D | siaddrlib.cpp | 2540 UINT_32 regArrayMode = gbTileMode.f.array_mode; in ReadGbTileMode()
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