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Searched refs:bank_swizzle (Results 1 – 14 of 14) sorted by relevance

/external/mesa3d/src/gallium/drivers/r600/
Dr700_asm.c61 S_SQ_ALU_WORD1_BANK_SWIZZLE(alu->bank_swizzle); in r700_bytecode_alu_build()
72 S_SQ_ALU_WORD1_BANK_SWIZZLE(alu->bank_swizzle) | in r700_bytecode_alu_build()
96 alu->bank_swizzle = G_SQ_ALU_WORD1_BANK_SWIZZLE(word1); in r700_bytecode_alu_read()
97 if (alu->bank_swizzle) in r700_bytecode_alu_read()
98 alu->bank_swizzle_force = alu->bank_swizzle; in r700_bytecode_alu_read()
Dr600_asm.c452 struct alu_bank_swizzle *bs, int bank_swizzle) in check_vector() argument
461 cycle = cycle_for_bank_swizzle_vec[bank_swizzle][src]; in check_vector()
482 struct alu_bank_swizzle *bs, int bank_swizzle) in check_scalar() argument
508 cycle = cycle_for_bank_swizzle_scl[bank_swizzle][src]; in check_scalar()
519 cycle = cycle_for_bank_swizzle_scl[bank_swizzle][src]; in check_scalar()
531 int bank_swizzle[5]; in check_and_set_bank_swizzle() local
539 slots[i]->bank_swizzle = slots[i]->bank_swizzle_force; in check_and_set_bank_swizzle()
555 bank_swizzle[i] = SQ_ALU_VEC_012; in check_and_set_bank_swizzle()
557 bank_swizzle[i] = slots[i]->bank_swizzle; in check_and_set_bank_swizzle()
559 bank_swizzle[4] = SQ_ALU_SCL_210; in check_and_set_bank_swizzle()
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Deg_asm.c259 S_SQ_ALU_WORD1_BANK_SWIZZLE(alu->bank_swizzle) | in eg_bytecode_alu_build()
277 S_SQ_ALU_WORD1_BANK_SWIZZLE(alu->bank_swizzle); in eg_bytecode_alu_build()
288 S_SQ_ALU_WORD1_BANK_SWIZZLE(alu->bank_swizzle) | in eg_bytecode_alu_build()
Dr600_asm.h59 unsigned bank_swizzle; member
/external/mesa3d/src/gallium/drivers/r600/sb/
Dsb_sched.cpp233 unsigned bs = n->bc.bank_swizzle; in unreserve()
261 unsigned bs = n->bc.bank_swizzle; in try_reserve()
491 n->bc.bank_swizzle = 0; in try_reserve()
494 n->bc.bank_swizzle = VEC_210; in try_reserve()
504 n->bc.bank_swizzle = bs; in try_reserve()
525 save_bs[i] = a->bc.bank_swizzle; in try_reserve()
529 a->bc.bank_swizzle = VEC_210; in try_reserve()
536 a->bc.bank_swizzle = 0; in try_reserve()
559 sblog << " bs: trying s" << i << " bs:" << a->bc.bank_swizzle in try_reserve()
565 sblog << " bs: reserved s" << i << " bs:" << a->bc.bank_swizzle in try_reserve()
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Dsb_bc_builder.cpp395 .BANK_SWIZZLE(bc.bank_swizzle) in build_alu()
422 .BANK_SWIZZLE(bc.bank_swizzle) in build_alu()
440 .BANK_SWIZZLE(bc.bank_swizzle) in build_alu()
455 .BANK_SWIZZLE(bc.bank_swizzle) in build_alu()
469 .BANK_SWIZZLE(bc.bank_swizzle) in build_alu()
485 .BANK_SWIZZLE(bc.bank_swizzle) in build_alu()
Dsb_bc_dump.cpp372 if (n.bc.bank_swizzle) { in dump()
375 s << " " << scl_bs[n.bc.bank_swizzle]; in dump()
377 s << " " << vec_bs[n.bc.bank_swizzle]; in dump()
Dsb_bc_decoder.cpp327 bc.bank_swizzle = iw1.get_BANK_SWIZZLE(); in decode_alu()
349 bc.bank_swizzle = w1.get_BANK_SWIZZLE(); in decode_alu()
366 bc.bank_swizzle = w1.get_BANK_SWIZZLE(); in decode_alu()
385 bc.bank_swizzle = w1.get_BANK_SWIZZLE(); in decode_alu()
Dsb_bc.h380 enum bank_swizzle { enum
510 unsigned bank_swizzle:3; member
/external/llvm/lib/Target/AMDGPU/
DR600InstrFormats.td107 bits<3> bank_swizzle;
114 let Word1{20-18} = bank_swizzle;
165 bits<3> bank_swizzle;
173 let Word1{20-18} = bank_swizzle;
DR600Packetizer.cpp306 AMDGPU::OpName::bank_swizzle); in addToPacket()
310 TII->getOperandIdx(MI.getOpcode(), AMDGPU::OpName::bank_swizzle); in addToPacket()
DEvergreenInstructions.td415 let bank_swizzle = 0;
465 BANK_SWIZZLE:$bank_swizzle),
487 BANK_SWIZZLE:$bank_swizzle),
519 LAST:$last, R600_Pred:$pred_sel, BANK_SWIZZLE:$bank_swizzle),
DR600Instructions.td99 BANK_SWIZZLE:$bank_swizzle),
103 "$pred_sel $bank_swizzle"),
142 BANK_SWIZZLE:$bank_swizzle),
147 "$pred_sel $bank_swizzle"),
183 BANK_SWIZZLE:$bank_swizzle),
189 "$bank_swizzle"),
440 let bank_swizzle = 5;
444 let bank_swizzle = 5;
DR600InstrInfo.cpp558 AMDGPU::OpName::bank_swizzle); in fitsReadPortLimitations()