| /external/mesa3d/src/gallium/winsys/radeon/drm/ |
| D | radeon_drm_surface.c | 154 surf_drm->bankw = surf_ws->bankw; in surf_winsys_to_drm()
195 surf_ws->bankw = surf_drm->bankw; in surf_drm_to_winsys()
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| D | radeon_drm_bo.c | 885 md->bankw = (args.tiling_flags >> RADEON_TILING_EG_BANKW_SHIFT) & RADEON_TILING_EG_BANKW_MASK; in radeon_bo_get_metadata()
913 args.tiling_flags |= (md->bankw & RADEON_TILING_EG_BANKW_MASK) << in radeon_bo_set_metadata()
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| /external/mesa3d/src/gallium/drivers/radeon/ |
| D | radeon_video.c | 157 wh = surfaces[i]->bankw * surfaces[i]->bankh; in rvid_join_surfaces()
169 surfaces[i]->bankw = surfaces[best_tiling]->bankw; in rvid_join_surfaces()
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| D | radeon_winsys.h | 238 unsigned bankw; member
323 unsigned bankw:4; /* max 8 */ member
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| D | r600_texture.c | 292 metadata->bankw = surface->bankw; in r600_texture_init_metadata()
599 fmask.bankw = rtex->surface.bankw; in r600_texture_get_fmask_info()
913 rtex->surface.surf_size, rtex->surface.surf_alignment, rtex->surface.bankw, in r600_print_texture_info()
1259 surface.bankw = metadata.bankw; in r600_texture_from_handle()
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| D | radeon_uvd.c | 1385 assert(luma->bankw == chroma->bankw); in ruvd_set_dt_surfaces()
1389 msg->body.decode.dt_surf_tile_config |= RUVD_BANK_WIDTH(bank_wh(luma->bankw)); in ruvd_set_dt_surfaces()
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| /external/libdrm/radeon/ |
| D | radeon_surface.c | 678 mtilew = (tilew * surf->bankw * surf_man->hw_info.num_pipes) * surf->mtilea; in eg_surface_init_2d()
763 switch (surf->bankw) { in eg_surface_sanity()
783 if ((tileb * surf->bankh * surf->bankw) < surf_man->hw_info.group_bytes) { in eg_surface_sanity()
922 surf->bankw = 1; in eg_surface_best()
927 if ((tileb * surf->bankh * surf->bankw) >= surf_man->hw_info.group_bytes) { in eg_surface_best()
1001 surf->bankw = 1; in eg_surface_best()
1016 if ((tileb * surf->bankh * surf->bankw) >= surf_man->hw_info.group_bytes) { in eg_surface_best()
1022 (surf->bankw * surf_man->hw_info.num_pipes)) >> 16; in eg_surface_best()
1324 surf->bankw = 1; in si_surface_sanity()
1402 …si_gb_tile_mode(gb_tile_mode, NULL, NULL, &surf->mtilea, &surf->bankw, &surf->bankh, &surf->tile_s… in si_surface_sanity()
[all …]
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| D | radeon_surface.h | 130 uint32_t bankw; member
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| /external/mesa3d/src/amd/vulkan/ |
| D | radv_radeon_winsys.h | 195 uint32_t bankw; member
238 unsigned bankw; member
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| D | radv_image.c | 443 metadata->bankw = surface->bankw; in radv_init_metadata()
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| /external/mesa3d/src/amd/vulkan/winsys/amdgpu/ |
| D | radv_amdgpu_surface.c | 407 surf->bankw && surf->bankh && surf->mtilea && surf->tile_split) { in radv_amdgpu_winsys_surface_init()
411 AddrTileInfoIn.bankWidth = surf->bankw; in radv_amdgpu_winsys_surface_init()
473 surf->bankw = AddrSurfInfoOut.pTileInfo->bankWidth; in radv_amdgpu_winsys_surface_init()
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| D | radv_amdgpu_bo.c | 268 tiling_flags |= AMDGPU_TILING_SET(BANK_WIDTH, util_logbase2(md->bankw)); in radv_amdgpu_winsys_bo_set_metadata()
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| /external/mesa3d/src/gallium/drivers/r600/ |
| D | evergreen_state.c | 670 unsigned macro_aspect, tile_split, bankh, bankw, nbanks, fmask_bankh; in evergreen_create_sampler_view_custom() local
770 bankw = tmp->surface.bankw; in evergreen_create_sampler_view_custom()
774 bankw = eg_bank_wh(bankw); in evergreen_create_sampler_view_custom()
865 S_03001C_BANK_WIDTH(bankw) | in evergreen_create_sampler_view_custom()
997 unsigned non_disp_tiling, macro_aspect, tile_split, bankh, bankw, fmask_bankh, nbanks; in evergreen_init_color_surface() local
1029 bankw = rtex->surface.bankw; in evergreen_init_color_surface()
1037 bankw = eg_bank_wh(bankw); in evergreen_init_color_surface()
1056 S_028C74_BANK_WIDTH(bankw) | in evergreen_init_color_surface()
1173 unsigned macro_aspect, tile_split, bankh, bankw, nbanks; in evergreen_init_depth_surface() local
1194 bankw = rtex->surface.bankw; in evergreen_init_depth_surface()
[all …]
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| /external/mesa3d/src/gallium/winsys/amdgpu/drm/ |
| D | amdgpu_surface.c | 439 surf->bankw && surf->bankh && surf->mtilea && surf->tile_split) { in amdgpu_surface_init()
445 AddrTileInfoIn.bankWidth = surf->bankw; in amdgpu_surface_init()
514 surf->bankw = AddrSurfInfoOut.pTileInfo->bankWidth; in amdgpu_surface_init()
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| D | amdgpu_bo.c | 620 md->bankw = 1 << AMDGPU_TILING_GET(tiling_flags, BANK_WIDTH); in amdgpu_buffer_get_metadata()
648 tiling_flags |= AMDGPU_TILING_SET(BANK_WIDTH, util_logbase2(md->bankw)); in amdgpu_buffer_set_metadata()
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