| /external/mesa3d/src/gallium/winsys/radeon/drm/ |
| D | radeon_drm_surface.c | 38 tileb = 8 * 8 * surf->bpe; in cik_get_macro_tile_index()
71 unsigned bpe) in surf_level_winsys_to_drm() argument
77 level_drm->pitch_bytes = level_ws->nblk_x * bpe; in surf_level_winsys_to_drm()
83 unsigned bpe) in surf_level_drm_to_winsys() argument
90 assert(level_drm->nblk_x * bpe == level_drm->pitch_bytes); in surf_level_drm_to_winsys()
95 unsigned flags, unsigned bpe, in surf_winsys_to_drm() argument
111 surf_drm->bpe = bpe; in surf_winsys_to_drm()
161 bpe * surf_drm->nsamples); in surf_winsys_to_drm()
188 surf_ws->bpe = surf_drm->bpe; in surf_drm_to_winsys()
204 surf_drm->bpe * surf_drm->nsamples); in surf_drm_to_winsys()
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| /external/libdrm/radeon/ |
| D | radeon_surface.c | 172 unsigned bpe, unsigned level, in surf_minify() argument
194 surflevel->pitch_bytes = surflevel->nblk_x * bpe * surf->nsamples; in surf_minify()
283 xalign = MAX2(1, surf_man->hw_info.group_bytes / surf->bpe); in r6_surface_init_linear()
287 xalign = MAX2((surf->bpe == 1) ? 64 : 32, xalign); in r6_surface_init_linear()
293 surf_minify(surf, surf->level+i, surf->bpe, i, xalign, yalign, zalign, offset); in r6_surface_init_linear()
314 xalign = MAX2(64, surf_man->hw_info.group_bytes / surf->bpe); in r6_surface_init_linear_aligned()
321 surf_minify(surf, surf->level+i, surf->bpe, i, xalign, yalign, zalign, offset); in r6_surface_init_linear_aligned()
340 xalign = surf_man->hw_info.group_bytes / (tilew * surf->bpe * surf->nsamples); in r6_surface_init_1d()
345 xalign = MAX2((surf->bpe == 1) ? 64 : 32, xalign); in r6_surface_init_1d()
354 surf_minify(surf, surf->level+i, surf->bpe, i, xalign, yalign, zalign, offset); in r6_surface_init_1d()
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| D | radeon_surface.h | 119 uint32_t bpe; member
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| /external/drm_gralloc/ |
| D | gralloc_drm_radeon.c | 81 static int radeon_get_pitch_align(struct radeon_info *info, int bpe, uint32_t tiling) in radeon_get_pitch_align() argument
88 pitch_align = (((info->group_bytes / 8) / bpe) * in radeon_get_pitch_align()
94 pitch_align = MAX(8, (info->group_bytes / (8 * bpe))); in radeon_get_pitch_align()
96 pitch_align = MAX(info->group_bytes / bpe, pitch_align); in radeon_get_pitch_align()
100 pitch_align = MAX(64, info->group_bytes / bpe); in radeon_get_pitch_align()
113 pitch_align = 256 / bpe; in radeon_get_pitch_align()
146 int bpe, uint32_t tiling) in radeon_get_base_align() argument
148 int pixel_align = radeon_get_pitch_align(info, bpe, tiling); in radeon_get_base_align()
154 base_align = MAX(info->num_banks * info->num_channels * 8 * 8 * bpe, in radeon_get_base_align()
155 pixel_align * bpe * height_align); in radeon_get_base_align()
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| /external/mesa3d/src/gallium/winsys/amdgpu/drm/ |
| D | amdgpu_surface.c | 290 tileb = 8 * 8 * surf->bpe; in cik_get_macro_tile_index()
302 unsigned flags, unsigned bpe, in amdgpu_surface_init() argument
333 surf->bpe = bpe; in amdgpu_surface_init()
366 switch (bpe) { in amdgpu_surface_init()
378 AddrDccIn.bpp = AddrSurfInfoIn.bpp = bpe * 8; in amdgpu_surface_init()
466 if (bpe == 2) in amdgpu_surface_init()
471 if (bpe == 1) in amdgpu_surface_init()
473 else if (bpe == 2) in amdgpu_surface_init()
475 else if (bpe == 4) in amdgpu_surface_init()
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| /external/mesa3d/src/amd/vulkan/winsys/amdgpu/ |
| D | radv_amdgpu_surface.c | 205 surf_level->pitch_bytes = AddrSurfInfoOut->pitch * (is_stencil ? 1 : surf->bpe); in radv_compute_level()
281 tileb = 8 * 8 * surf->bpe; in cik_get_macro_tile_index()
347 switch (surf->bpe) { in radv_amdgpu_winsys_surface_init()
358 AddrDccIn.bpp = AddrSurfInfoIn.bpp = surf->bpe * 8; in radv_amdgpu_winsys_surface_init()
432 if (surf->bpe == 2) in radv_amdgpu_winsys_surface_init()
437 if (surf->bpe == 1) in radv_amdgpu_winsys_surface_init()
439 else if (surf->bpe == 2) in radv_amdgpu_winsys_surface_init()
441 else if (surf->bpe == 4) in radv_amdgpu_winsys_surface_init()
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| /external/mesa3d/src/gallium/drivers/radeon/ |
| D | r600_texture.c | 56 if (rdst->surface.bpe != rsrc->surface.bpe) in r600_prepare_for_dma_blit()
187 box->x / rtex->surface.blk_w) * rtex->surface.bpe; in r600_texture_get_offset()
205 unsigned i, bpe, flags = 0; in r600_init_surface() local
212 bpe = 4; /* stencil is allocated separately on evergreen */ in r600_init_surface()
214 bpe = util_format_get_blocksize(ptex->format); in r600_init_surface()
216 if (bpe == 3) { in r600_init_surface()
217 bpe = 4; in r600_init_surface()
230 bpe = 4; in r600_init_surface()
259 r = rscreen->ws->surface_init(rscreen->ws, ptex, flags, bpe, in r600_init_surface()
266 pitch_in_bytes_override != surface->level[0].nblk_x * bpe) { in r600_init_surface()
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| D | radeon_vce_40_2_2.c | 97 RVCE_CS(enc->luma->level[0].nblk_x * enc->luma->bpe); // encRefPicLumaPitch in create()
98 RVCE_CS(enc->chroma->level[0].nblk_x * enc->chroma->bpe); // encRefPicChromaPitch in create()
327 RVCE_CS(enc->luma->level[0].nblk_x * enc->luma->bpe); // encInputPicLumaPitch in encode()
328 RVCE_CS(enc->chroma->level[0].nblk_x * enc->chroma->bpe); // encInputPicChromaPitch in encode()
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| D | radeon_vce_50.c | 134 RVCE_CS(enc->luma->level[0].nblk_x * enc->luma->bpe); // encInputPicLumaPitch in encode()
135 RVCE_CS(enc->chroma->level[0].nblk_x * enc->chroma->bpe); // encInputPicChromaPitch in encode()
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| D | radeon_winsys.h | 301 unsigned bpe:5; member
744 unsigned flags, unsigned bpe,
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| D | radeon_vce_52.c | 180 RVCE_CS(enc->luma->level[0].nblk_x * enc->luma->bpe); // encRefPicLumaPitch in create()
181 RVCE_CS(enc->chroma->level[0].nblk_x * enc->chroma->bpe); // encRefPicChromaPitch in create()
247 RVCE_CS(enc->luma->level[0].nblk_x * enc->luma->bpe); // encInputPicLumaPitch in encode()
248 RVCE_CS(enc->chroma->level[0].nblk_x * enc->chroma->bpe); // encInputPicChromaPitch in encode()
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| D | radeon_vce.c | 227 unsigned pitch = align(enc->luma->level[0].nblk_x * enc->luma->bpe, 128); in rvce_frame_offset()
459 cpb_size = align(tmp_surf->level[0].nblk_x * tmp_surf->bpe, 128); in rvce_create_encoder()
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| D | radeon_uvd.c | 1356 msg->body.decode.dt_pitch = luma->level[0].nblk_x * luma->bpe; in ruvd_set_dt_surfaces()
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| /external/mesa3d/src/amd/vulkan/ |
| D | radv_image.c | 73 surface->bpe = vk_format_get_blocksize(pCreateInfo->format); in radv_init_surface()
75 if (surface->bpe == 3) { in radv_init_surface()
76 surface->bpe = 4; in radv_init_surface()
482 fmask.bpe = 1; in radv_image_get_fmask_info()
485 fmask.bpe = 4; in radv_image_get_fmask_info()
743 image->surface.level[0].nblk_x = create_info->stride / image->surface.bpe; in radv_image_create()
848 switch (image->surface.bpe) { in radv_image_set_optimal_micro_tile_mode()
861 switch (image->surface.bpe) { in radv_image_set_optimal_micro_tile_mode()
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| D | radv_radeon_winsys.h | 184 uint32_t bpe; member
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| D | radv_device.c | 1705 if (iview->image->surface.bpe == 1) in radv_initialise_color_surface()
1707 else if (iview->image->surface.bpe == 2) in radv_initialise_color_surface()
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| /external/swiftshader/third_party/LLVM/lib/Analysis/ |
| D | ProfileVerifierPass.cpp | 247 const_pred_iterator bpi = pred_begin(BB), bpe = pred_end(BB); in recurseBasicBlock() local
249 if (bpi == bpe) { in recurseBasicBlock()
253 for (;bpi != bpe; ++bpi) { in recurseBasicBlock()
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| /external/mesa3d/src/gallium/drivers/radeonsi/ |
| D | si_dma.c | 270 bpp = rdst->surface.bpe; in si_dma_copy()
271 dst_pitch = rdst->surface.level[dst_level].nblk_x * rdst->surface.bpe; in si_dma_copy()
272 src_pitch = rsrc->surface.level[src_level].nblk_x * rsrc->surface.bpe; in si_dma_copy()
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| D | cik_sdma.c | 128 return (set_bpp ? util_logbase2(tex->surface.bpe) : 0) | in encode_tile_info()
151 unsigned bpp = rdst->surface.bpe; in cik_sdma_copy_texture()
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| D | si_blit.c | 874 unsigned blocksize = rsrc->surface.bpe; in si_resource_copy_region()
916 unsigned blocksize = rsrc->surface.bpe; in si_resource_copy_region()
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| D | si_state.c | 2176 if (rtex->surface.bpe == 1) in si_initialize_color_surface()
2178 else if (rtex->surface.bpe == 2) in si_initialize_color_surface()
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| /external/mesa3d/src/gallium/drivers/r600/ |
| D | r600_state.c | 2948 bpp = rdst->surface.bpe; in r600_dma_copy()
2949 dst_pitch = rdst->surface.level[dst_level].nblk_x * rdst->surface.bpe; in r600_dma_copy()
2950 src_pitch = rsrc->surface.level[src_level].nblk_x * rsrc->surface.bpe; in r600_dma_copy()
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| D | evergreen_state.c | 3493 bpp = rdst->surface.bpe; in evergreen_dma_copy()
3494 dst_pitch = rdst->surface.level[dst_level].nblk_x * rdst->surface.bpe; in evergreen_dma_copy()
3495 src_pitch = rsrc->surface.level[src_level].nblk_x * rsrc->surface.bpe; in evergreen_dma_copy()
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