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Searched refs:chip_class (Results 1 – 25 of 60) sorted by relevance

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/external/mesa3d/src/gallium/winsys/radeon/drm/
Dradeon_drm_winsys.c230 ws->info.chip_class = R300; in do_winsys_init()
241 ws->info.chip_class = R400; in do_winsys_init()
249 ws->info.chip_class = R500; in do_winsys_init()
259 ws->info.chip_class = R600; in do_winsys_init()
265 ws->info.chip_class = R700; in do_winsys_init()
278 ws->info.chip_class = EVERGREEN; in do_winsys_init()
282 ws->info.chip_class = CAYMAN; in do_winsys_init()
289 ws->info.chip_class = SI; in do_winsys_init()
296 ws->info.chip_class = CIK; in do_winsys_init()
327 if (ws->info.chip_class >= EVERGREEN && ws->info.drm_minor >= 27) { in do_winsys_init()
[all …]
/external/mesa3d/src/amd/vulkan/
Dsi_cmd_buffer.c149 if (physical_device->rad_info.chip_class < CIK) in si_write_harvested_raster_configs()
158 if (physical_device->rad_info.chip_class >= CIK) in si_write_harvested_raster_configs()
163 if (physical_device->rad_info.chip_class < CIK) in si_write_harvested_raster_configs()
189 if (physical_device->rad_info.chip_class >= CIK) { in si_init_compute()
204 if (physical_device->rad_info.chip_class <= SI) { in si_init_compute()
239 if (physical_device->rad_info.chip_class < CIK) in si_init_config()
337 if (physical_device->rad_info.chip_class >= CIK) in si_init_config()
374 if (physical_device->rad_info.chip_class >= CIK) { in si_init_config()
411 if (physical_device->rad_info.chip_class >= VI) { in si_init_config()
521 enum chip_class chip_class = cmd_buffer->device->physical_device->rad_info.chip_class; in si_get_ia_multi_vgt_param() local
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/external/mesa3d/src/gallium/drivers/radeonsi/
Dsi_pipe.c190 sscreen->b.chip_class != SI && in si_create_context()
238 if (sctx->b.chip_class >= CIK) in si_create_context()
259 if (sctx->b.chip_class == CIK) { in si_create_context()
325 (sscreen->b.chip_class >= CIK || in si_have_tgsi_compute()
429 return sscreen->b.chip_class < CIK || in si_get_param()
761 sscreen->b.chip_class = sscreen->b.info.chip_class = VI; in si_handle_env_var_force_family()
763 sscreen->b.chip_class = sscreen->b.info.chip_class = CIK; in si_handle_env_var_force_family()
765 sscreen->b.chip_class = sscreen->b.info.chip_class = SI; in si_handle_env_var_force_family()
814 sscreen->b.chip_class >= VI && in radeonsi_screen_create()
819 (sscreen->b.chip_class == VI && in radeonsi_screen_create()
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Dsi_state_draw.c158 hardware_lds_size = sctx->b.chip_class >= CIK ? 65536 : 32768; in si_emit_derived_tess_state()
173 if (sctx->b.chip_class == SI) { in si_emit_derived_tess_state()
186 if (sctx->b.chip_class >= CIK) { in si_emit_derived_tess_state()
198 if (sctx->b.chip_class == CIK && sctx->b.family != CHIP_HAWAII) in si_emit_derived_tess_state()
244 if (sctx->b.chip_class >= CIK) in si_emit_derived_tess_state()
323 if (sctx->b.chip_class >= CIK) { in si_get_ia_multi_vgt_param()
356 if (sctx->b.chip_class <= VI && in si_get_ia_multi_vgt_param()
370 (sctx->b.chip_class == VI && in si_get_ia_multi_vgt_param()
409 S_028AA8_WD_SWITCH_ON_EOP(sctx->b.chip_class >= CIK ? wd_switch_on_eop : 0) | in si_get_ia_multi_vgt_param()
410 S_028AA8_MAX_PRIMGRP_IN_WAVE(sctx->b.chip_class >= VI ? in si_get_ia_multi_vgt_param()
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Dcik_sdma.c219 (sctx->b.chip_class != CIK || in cik_sdma_copy_texture()
245 if (sctx->b.chip_class == CIK) { in cik_sdma_copy_texture()
302 if (sctx->b.chip_class == CIK && in cik_sdma_copy_texture()
409 if (sctx->b.chip_class == CIK) { in cik_sdma_copy_texture()
434 (sctx->b.chip_class == VI && in cik_sdma_copy_texture()
473 (sctx->b.chip_class != CIK || in cik_sdma_copy_texture()
503 if (sctx->b.chip_class == CIK) { in cik_sdma_copy_texture()
Dsi_cp_dma.c79 if (sctx->b.chip_class >= CIK) { in si_emit_cp_dma()
118 (sctx->b.chip_class == SI ? SI_CONTEXT_INV_GLOBAL_L2 : 0); in get_flush_flags()
128 sctx->b.chip_class >= CIK ? CP_DMA_USE_L2 : 0; in get_tc_l2_flag()
404 assert(sctx->b.chip_class >= CIK); in cik_prefetch_TC_L2_async()
/external/mesa3d/src/gallium/drivers/r600/
Dr600_hw_context.c73 if (ctx->b.chip_class == R600) { in r600_need_cs_space()
134 if (rctx->b.chip_class >= R700 && in r600_flush_emit()
140 if (rctx->b.chip_class >= R700 && in r600_flush_emit()
155 (rctx->b.chip_class == R600 && rctx->b.flags & R600_CONTEXT_STREAMOUT_FLUSH)) { in r600_flush_emit()
181 if (rctx->b.chip_class >= R700 && in r600_flush_emit()
191 if (rctx->b.chip_class >= R700 && in r600_flush_emit()
203 if (rctx->b.chip_class >= EVERGREEN) in r600_flush_emit()
210 if (rctx->b.chip_class >= R700 && in r600_flush_emit()
278 if (ctx->b.chip_class == R600) { in r600_context_gfx_flush()
320 if (ctx->b.chip_class <= EVERGREEN) { in r600_begin_new_cs()
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Dr600_isa.h693 r600_isa_alu_opcode(enum r600_chip_class chip_class, unsigned op) { in r600_isa_alu_opcode() argument
694 int opc = r600_isa_alu(op)->opcode[chip_class >> 1]; in r600_isa_alu_opcode()
700 r600_isa_alu_slots(enum r600_chip_class chip_class, unsigned op) { in r600_isa_alu_slots() argument
701 unsigned slots = r600_isa_alu(op)->slots[chip_class]; in r600_isa_alu_slots()
707 r600_isa_fetch_opcode(enum r600_chip_class chip_class, unsigned op) { in r600_isa_fetch_opcode() argument
708 int opc = r600_isa_fetch(op)->opcode[chip_class]; in r600_isa_fetch_opcode()
714 r600_isa_cf_opcode(enum r600_chip_class chip_class, unsigned op) { in r600_isa_cf_opcode() argument
715 int opc = r600_isa_cf(op)->opcode[chip_class]; in r600_isa_cf_opcode()
Dr600_asm.c144 enum chip_class chip_class, in r600_bytecode_init() argument
152 if ((chip_class == R600) && in r600_bytecode_init()
162 bc->chip_class = chip_class; in r600_bytecode_init()
325 int max_slots = bc->chip_class == CAYMAN ? 4 : 5; in assign_alu_units()
412 if (bc->chip_class >= R700) { in reserve_cfile()
533 boolean scalar_only = bc->chip_class == CAYMAN ? false : true; in check_and_set_bank_swizzle()
534 int max_slots = bc->chip_class == CAYMAN ? 4 : 5; in check_and_set_bank_swizzle()
612 int max_slots = bc->chip_class == CAYMAN ? 4 : 5; in replace_gpr_with_pv_ps()
648 if (bc->chip_class < CAYMAN) { in replace_gpr_with_pv_ps()
764 int max_slots = bc->chip_class == CAYMAN ? 4 : 5; in merge_inst_groups()
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Dr600_asm.h226 enum chip_class chip_class; member
262 enum chip_class chip_class,
Dr600_pipe.c150 switch (rctx->b.chip_class) { in r600_create_context()
156 rctx->custom_blend_resolve = rctx->b.chip_class == R700 ? r700_create_resolve_blend(rctx) in r600_create_context()
183 R600_ERR("Unsupported chip class %d.\n", rctx->b.chip_class); in r600_create_context()
298 return rscreen->b.chip_class > R700; in r600_get_param()
464 return rscreen->b.chip_class >= R700; in r600_get_param()
627 if (rscreen->b.info.chip_class >= EVERGREEN) { in r600_screen_create()
648 switch (rscreen->b.chip_class) { in r600_screen_create()
669 switch (rscreen->b.chip_class) { in r600_screen_create()
Dr600_uvd.c83 if (ctx->b.chip_class < EVERGREEN || tmpl->interlaced || !R600_UVD_ENABLE_TILING) in r600_video_buffer_create()
92 if (ctx->b.chip_class < EVERGREEN || tmpl->interlaced || !R600_UVD_ENABLE_TILING) in r600_video_buffer_create()
102 if (ctx->b.chip_class < EVERGREEN || tmpl->interlaced || !R600_UVD_ENABLE_TILING) in r600_video_buffer_create()
Dr600_state_common.c84 if (rctx->b.chip_class >= EVERGREEN && a->cb0_export_16bpc) { in r600_emit_alphatest_state()
178 if (rctx->b.chip_class <= R700 && in r600_bind_blend_state_internal()
319 if (rctx->b.chip_class >= EVERGREEN) { in r600_bind_dsa_state()
465 if (rctx->b.chip_class <= R700 && in r600_bind_sampler_states()
538 rctx->vertex_buffer_state.atom.num_dw = (rctx->b.chip_class >= EVERGREEN ? 12 : 11) * in r600_vertex_buffers_dirty()
594 state->atom.num_dw = (rctx->b.chip_class >= EVERGREEN ? 14 : 13) * in r600_sampler_views_dirty()
659 if (rctx->b.chip_class <= R700 && in r600_set_sampler_views()
1052 state->atom.num_dw = rctx->b.chip_class >= EVERGREEN ? util_bitcount(state->dirty_mask)*20 in r600_constant_buffers_dirty()
1556 if (rctx->b.chip_class <= R700) { in r600_update_derived_state()
1569 if (rctx->b.chip_class >= EVERGREEN) in r600_update_derived_state()
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Deg_asm.c93 if (bc->chip_class == EVERGREEN) /* no EOP on cayman */ in eg_bytecode_cf_build()
108 if (bc->chip_class == EVERGREEN) /* no EOP on cayman */ in eg_bytecode_cf_build()
155 assert(bc->chip_class >= EVERGREEN); in egcm_load_index_reg()
164 if (bc->chip_class == CAYMAN) in egcm_load_index_reg()
174 if (bc->chip_class == EVERGREEN) { in egcm_load_index_reg()
Devergreen_compute.c427 if (rctx->b.chip_class < CAYMAN) { in evergreen_emit_dispatch()
466 if (rctx->b.chip_class == EVERGREEN) in compute_emit_cs()
535 if (rctx->b.chip_class >= CAYMAN) { in compute_emit_cs()
778 if (rctx->b.chip_class < CAYMAN) in evergreen_init_atom_start_compute_cs()
779 evergreen_init_common_regs(rctx, cb, rctx->b.chip_class, rctx->b.family, in evergreen_init_atom_start_compute_cs()
782 cayman_init_common_regs(cb, rctx->b.chip_class, rctx->b.family, in evergreen_init_atom_start_compute_cs()
789 if (rctx->b.chip_class < CAYMAN) { in evergreen_init_atom_start_compute_cs()
839 if (rctx->b.chip_class < CAYMAN) { in evergreen_init_atom_start_compute_cs()
850 if (rctx->b.chip_class < CAYMAN) { in evergreen_init_atom_start_compute_cs()
/external/mesa3d/src/gallium/drivers/radeon/
Dr600_pipe_common.c109 if (ctx->chip_class == CIK || in r600_gfx_write_event_eop()
110 ctx->chip_class == VI) { in r600_gfx_write_event_eop()
139 if (screen->chip_class == CIK || in r600_gfx_write_fence_dwords()
140 screen->chip_class == VI) in r600_gfx_write_fence_dwords()
232 if (rctx->chip_class >= CIK) in r600_dma_emit_wait_idle()
234 else if (rctx->chip_class >= EVERGREEN) in r600_dma_emit_wait_idle()
562 rctx->chip_class = rscreen->chip_class; in r600_common_context_init()
564 if (rscreen->chip_class >= CIK) in r600_common_context_init()
566 else if (rscreen->chip_class >= EVERGREEN) in r600_common_context_init()
584 if ((rscreen->chip_class == EVERGREEN || rscreen->chip_class == CAYMAN) && in r600_common_context_init()
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Dr600_streamout.c93 if (rctx->chip_class >= SI) { in r600_streamout_buffers_dirty()
160 if (rctx->chip_class >= CIK) { in r600_flush_vgt_streamout()
162 } else if (rctx->chip_class >= EVERGREEN) { in r600_flush_vgt_streamout()
168 if (rctx->chip_class >= CIK) { in r600_flush_vgt_streamout()
201 if (rctx->chip_class >= SI) { in r600_emit_streamout_begin()
324 if (rctx->chip_class >= EVERGREEN) { in r600_emit_streamout_enable()
Dr600_viewport.c28 #define GET_MAX_SCISSOR(rctx) (rctx->chip_class >= EVERGREEN ? 16384 : 8192)
121 if (rctx->chip_class == EVERGREEN || rctx->chip_class == CAYMAN) { in evergreen_apply_scissor_bug_workaround()
127 if (rctx->chip_class == CAYMAN && in evergreen_apply_scissor_bug_workaround()
160 #define GET_MAX_VIEWPORT_RANGE(rctx) (rctx->chip_class >= EVERGREEN ? 32768 : 16384)
202 if (rctx->chip_class >= CAYMAN) in r600_emit_guardband()
Dr600_texture.c210 if (rscreen->chip_class >= EVERGREEN && !is_flushed_depth && in r600_init_surface()
238 if (rscreen->chip_class >= VI && in r600_init_surface()
335 if (rscreen->chip_class >= SI) in r600_texture_discard_cmask()
426 if (rctx->chip_class < SI) in r600_degrade_tile_mode_to_linear()
597 if (rscreen->chip_class <= CAYMAN) { in r600_texture_get_fmask_info()
624 if (rscreen->chip_class <= R700) { in r600_texture_get_fmask_info()
742 if (rscreen->chip_class >= SI) { in r600_texture_allocate_cmask()
751 if (rscreen->chip_class >= SI) in r600_texture_allocate_cmask()
765 if (rscreen->chip_class >= SI) { in r600_texture_alloc_cmask_separate()
783 if (rscreen->chip_class >= SI) in r600_texture_alloc_cmask_separate()
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/external/mesa3d/src/amd/common/
Dac_debug.c142 int trace_id, enum chip_class chip_class, in ac_parse_packet3() argument
195 if (chip_class >= CIK) { in ac_parse_packet3()
271 trace_id, name, chip_class, in ac_parse_packet3()
341 const char *name, enum chip_class chip_class, in ac_parse_ib() argument
352 chip_class, addr_callback, in ac_parse_ib()
Dac_debug.h43 const char *name, enum chip_class chip_class,
Dac_nir_to_llvm.h57 enum chip_class chip_class; member
/external/mesa3d/src/amd/vulkan/winsys/amdgpu/
Dradv_amdgpu_surface.h31 …u_addr_create(struct amdgpu_gpu_info *amdinfo, int family, int rev_id, enum chip_class chip_class);
Dradv_amdgpu_winsys.c193 ws->info.chip_class = VI; in do_winsys_init()
195 ws->info.chip_class = CIK; in do_winsys_init()
197 ws->info.chip_class = SI; in do_winsys_init()
278 ws->addrlib = radv_amdgpu_addr_create(&ws->amdinfo, ws->family, ws->rev_id, ws->info.chip_class); in do_winsys_init()
325 if (ws->info.chip_class == SI) in do_winsys_init()
Dradv_amdgpu_surface.c115 enum chip_class chip_class) in radv_amdgpu_addr_create() argument
133 if (chip_class == SI) { in radv_amdgpu_addr_create()
271 if (info->chip_class >= CIK) in radv_set_micro_tile_mode()
430 if (ws->info.chip_class == SI) { in radv_amdgpu_winsys_surface_init()

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